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MSP430F5528: The fall time of my I2C, SCL and SDA signals are too fast for the slave device on my bus.

oldViking
Expert 1160 points
Part Number: MSP430F5528

High,    I am using the UCB1 peripheral in the I2C mode, via the TI-RTOS driver.  The module is always operated as a master with one slave device on the bus. 

My slave device specifies a minimum fall time of 20 nS, a maximum rise time of 300 nS,  on the SCL and SDA signals.  Both of my pullup resistors are 3.32K ohms and are connected to the 3.00V supply.

Using my scope I have measured a fall time of 1.8 nS on both of these signals.  Using the emulator, I have checked the drive strength settings in the register P4DS.  The register has a value of 0x00, indicating that P4.1 and P4.2 are both set for reduced drive strength.

Attempting to increase the fall time, I connected a 47 pF cap between each signal and ground.  Now I measure a fall time of 4nS on both signals. Still way too fast.

 My rise time is good at 172 nS.

What is the best way for me to achieve the correct fall time ?

Thank you for your time.

Roy

  • 0
    TI__Guru**** 211887 points
    Hi Roy,

    You can try to reduce the SCL clock frequency, other than that I do not believe that there is anything more that can be done on a software/register level. Do you notice this fast fall time affecting I2C communication with your slave device? You can try increasing the pulldown capacitance or decreasing the pullup resistance. Typically the opposite problem is encountered, where the fall/rise time is too slow.

    Regards,
    Ryan
  • 0
    Guru 46710 points
    It is very unusual for IC to *require* slow rise or fall time for signals. Could you please tell which chip you are talking about - so we can check datasheet? No single i2c device I am familiar with, specify minimum SCL/SDA fall or rise time for *incoming* signals. I believe that everything will be fine even if you do nothing about it. Yes, capacitor is only solution which could be used for i2c because any series resistor will change signal levels.

    > Typically the opposite problem is encountered, where the fall/rise time is too slow.
    Could not agree more.
  • 0 in reply to Ilmars
    Expert 1160 points

    Hi,

    I am using an LTC2485.  The bus seems to be functioning very well when I look at it on the scope.    The part that has me worried is that the lower 12 bits seem to be noise.  So my best theory at this point is that, because of the fast fall time,  bits are being corrupted internally on the LTC2485.

    I am going to contact LTC and see if my theory has any credence.  

    Roy

  • 0 in reply to oldViking
    Guru 46710 points

    Roy Nordstrom1 said:
    The part that has me worried is that the lower 12 bits seem to be noise.

    This is easy to test. - Short both inputs and see what is coming out of ADC. Did you do all the decoupling of supply, reference and inputs as required? - Those 12 bits of noise could be just noise of your circuit :) Actually you can try to slow down fall time by adding 20..30 ohm series resistors at CPU end in addition to cap on bus, also try to slow down i2c speed (clock freq) and see how it goes.

    Roy Nordstrom1 said:
    I am going to contact LTC and see if my theory has any credence.  

    Good idea. Nothing much more we can help here. After all - if they *require* limited I2C rise/fall time for their device, then they shall be able to tell how to do it properly.

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