Is it possible to use a 16MHz external crystal (connected to XIN/XOUT) as a reference for a 24MHz CPU clock on the F5151?
Thanks,
Skyler
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Is it possible to use a 16MHz external crystal (connected to XIN/XOUT) as a reference for a 24MHz CPU clock on the F5151?
Thanks,
Skyler
Yes, XT1CLK can be chosen for high-frequency 16 MHz operation (XTS = 1, XT1DRIVE = 2, OSCOFF = XT1BYPASS = XT1OFF = 0) and is selectable as the FLL reference clock source (SELREF = 0) and can then be divided by 16 (FLLREFDIV = 5) and multiplied by 24 (FLLN = 23) to settle the DCO frequency at 24 MHz. Make sure that PMMCOREV is stepped up to 3 level-by-level.
Regards,
Ryan
Thanks Ryan. What I'm trying to do now is run MCLK at 24MHz (referenced from XT1) and run SMCLK at 16 MHz directly from XT1.
Here is the code I'm using currently:
bspMcuSetVCore(1); bspMcuSetVCore(2); bspMcuSetVCore(3); UCSCTL6 &= ~(XT1OFF | XT1BYPASS); // XT1 On UCSCTL6 |= ( XTS + XT1DRIVE_2); // Internal load cap UCSCTL3 = FLLREFDIV2 + FLLREFDIV0; // FLL Reference Clock = XT1 UCSCTL4 |= SELM_0; // MCLK = X1 (by default) UCSCTL2 = 23 + FLLD_1; // Loop until XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle do { UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag
From this, I'm seeing a 16 MHz MCLK and SMCLK. Can you help me get the MCLK running at 24MHz?
Thanks,
Skyler
Thanks Vikas and Ryan.
The reason for sourcing the MCLK from XT1 is that we need it to be better than 100 ppm over temperature at 24 MHz. Currently, the customer is using a 16 MHz crystal, so we may just replace it with a 24 MHz crystal to make things smoother.
Skyler
Ryan,
This is for a Sigfox application, which requires extremely accurate timing of the MCLK and 8 MHz SPI clock (which we are sourcing from SMCLK). We've found that using the internal reference has caused us issues with delays between SPI writing, and affects both the BPSK timing and the spectral mask.
In our original design, we multiply a 32kHz crystal to run at 24 MHz MCLK and SMCLK and divide the SPI clock by 3, but we wanted to work with what the customer already designed on their board. We'll switch to 24 MHz XT1 for both MCLK and SMCLK, dividing SMCLK by 3 for the SPI clock. Thanks for your help!
Skyler
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