MSP430FR2311: Migration from MSP430g2332 to MSP430FR2311

Hi Destin,

To ensure the FLL can be locked, DCO software trim is recommended for the target clock frequencies other than the maximum valid values(It's 16MHz for FR2311). You can find the section 3.2.11 of the MSP430FR4xx and MSP430FR2xx Family User's Guide for the trim guide.

We also provide a code example msp430fr231x_CS_07.c to show how to configure MCLK for 1MHz and use DCO software trim to lock FLL. You can modify the parameter of macro definition  MCLK_FREQ_MHZ and reuse the function Software_Trim() for your target clock frequency.

An example for 8MHz target clock frequency:

Step 1: modify the macro in line72

#define MCLK_FREQ_MHZ    1 ==> #define MCLK_FREQ_MHZ   8

Step 2: Configure the DCO to your target frequency, such as line77~82 of the code example.

Step 3: Call the Software_Trim() after enable the FLL(line82). Taking an example below:

    CSCTL3 |= SELREF__REFOCLK;              // Set REFO as FLL reference source
    CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz
    CSCTL2 = FLLD_0 + 243;                  // DCODIV = 8MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                // enable FLL
    Software_Trim();                        // Software Trim to get the best DCOFTRIM value

Wei,

MSP Customer Applications