Other Parts Discussed in Thread: MSP430G2955
Microprocessor used MSP430F5247, migrating from an earlier revision using the MSP430G2955. I am programming in C with CCS 6.1.
The circuit portion below shows the power management circuit involved.
The device is woken by RF energy from a device trying to communicate with it, the ENERGISE signal on the gate of Q3B. The microprocessor latches the power early in the start-up sequence, driving VACT_LA high. The new processor takes longer to stabilise the DCO than the old one, and the energise signal would sometimes collapse before the microprocessor would successfully latch the power on. The issue was solved by putting the latch ahead of starting the DCO with the FLL.
However when the energise circuit collapsed too soon for the latch to hold the microprocessor would sometimes enter a limbo state. Connecting to it with debug in CCS, as a running target, I was able to check the registers and found that the CPU and oscillator were off. The watchdog was functioning but with the maximum interval. I fixed the watchdog issue first, so that the micro would reset soon after getting into this state. Then went on to sort out the real problem of getting the latch happening sooner. Problem solved, almost.
This brings me to my question. How did the microprocessor get into this state?
I have tested the BOR simulating battery failure as part of acceptance testing and found no issues. I can only imagine the microprocessor has a brown-out of sorts when the latching of the power falters. However a complete brown-out should drop the latch and the microprocessor would have to wait for the next transmitted packet to attempt to power up.
Jeff