MSP430F2618: Clarifying Question about USCI-B I2C Module, Master-Receiver Mode

Hi,

I am writing a custom I2C driver for my project, and I am trying to make sure that I understand exactly every part of the MSP430's I2C module.  Several pieces of documentation are confusing me on one point, as they seem to give conflicting descriptions of the precise order of certain operations - or are at least vague enough that I'm not sure what they mean.

Particularly, I want to know at exactly what time, when the MSP is configured as a master-receiver, the I2C module sends an ACK.  As far as I can tell, a generalized RX transaction looks like this:

(1) initialization (master sends start condition with slave address, slave ACKs its address, etc.) -> (2) [slave] transmits byte -> (3) [master] moves received byte from shift register into UCBxRXBUF, software reads UCBxRXBUF, master sends ACK, maybe clock is held waiting for software somewhere in there -> (4) [slave] transmits next byte.

I'm unsure, however, what happens in step 3.  According to the MSP430 family user guide (SLAU144J), in both the text of section 17.3.4.2.2 and figure 17-13, it looks like this

(1) initialization -> (2) [slave] transmits byte -> (3) [master] sets UCBRXIFG immediately on byte in shift register -> (3.5) [master] moves byte from shift register to RXBUF -> (4) [master] module holds bus low until RXBUF is read -> (5) [software] read RXBUF -> (6) [master] RXIFG reset -> (7) [master] sends ACK -> (8) [slave] transmits byte

Step 4 is implied by text reading "If UCBxRXBUF is not read the master holds the bus during reception of the last data bit and until the UCBxRXBUF is read."  However, in the same text, it also seems to imply that the order is like this:

(1) initialization -> (2) [slave] transmits byte -> (3) [master] sets UCBRXIFG immediately on byte in shift register -> (3.5) [master] moves byte from shift register to RXBUF -> (4) [master] sends ACK -> (5) [master] module holds bus low until RXBUF is read? -> (6) [slave] transmits byte -> (7) [software] read RXBUF -> (8) [master] RXIFG reset

The location of steps 3, 3.5, and 4 are implied by the text reading "After the acknowledge of the address from the slave the first data byte from the slave is received and acknowledged and the UCBxRXIFG flag is set."  The rest of the steps are ordered around that, considering how they must be if 3 and 4 are where they are.  This ordering also seems to be upheld by the errata document (SLAZ188L) for the chip, in error USCI-30, stating "once the first byte is moved form the receive shift register to the receive buffer, the byte is acknowledged and the state machine allows the reception of the next byte."

As I'm trying to make my driver robust so as to catch all possible errors in use (it's in a system that cannot be easily accessed during operation to correct errors), I'd like to know exactly what the order is, so that I know exactly what my timing constraints are, etc.

Thank you,

John