CCS/MSP430FR2310: I2C at 400kHz sourced from SMCLK, MSP430 is Master, using read data from slave as a condition.

Tool/software: Code Composer Studio

Hello,

Several months ago I began thisthread to receive help in using an MSP430 master to write to a slave device over I2C. I am currently trying to adjust the solution to new requirements: currently, the MSP430 is able to write to the slave device after a time delay. Now, however, it also needs to read a response from the slave, and if the first two bytes of that response equal 0xF0, the GPIO on P1.1 goes to logic high, otherwise the MSP430 writes to the slave again and checks the response. We have confirmed that the slave is responding with the expected data, and have observed that GPIO pin gives a 3.3V high if the

P1OUT ^= BIT0;

is given in the first while loop, but only about 1.6V when the IF statement is reversed (it is in the second while loop). Are there any glaring issues with the code that I wrote for this implementation? :

//MSP430 UHF Antenna Deployment Code

//VERSION 2

//Author: Brendan Scobie

#include <msp430.h>


unsigned char TXData[]= {0x1F}; // Pointer to TX Data
volatile unsigned char RXData;
unsigned char DataLength = sizeof(TXData);
unsigned char TXByteCtr;
unsigned char SlaveFlag = 0;
unsigned char AllOn[]={0xF0}; //A transmission from the slave antenna that has as its first two bytes 0xF0 indicates that all antennae are deployed

/**
* main.c
*/
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

// Configure GPIO
P1OUT &= ~BIT0;                         // Clear P1.0 output latch
P1DIR |= BIT0;                          // For LED

__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_3;// DCOFTRIM=3, DCO Range = 8MHz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL

CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
// default DCODIV as MCLK and SMCLK source

CSCTL5 = DIVS__4; // Scale SMCLK down to 2Mhz

//P1OUT = 0;
//P1DIR = 0xff;

//P2OUT = 0;
//P2DIR = 0xff;

//#if 0
// If using default I2C pins
P1SEL0 = (BIT2 | BIT3);
P1SEL1 = 0;
//#else
// Map to alternate pins
//P2SEL0 = (BIT4 | BIT5);
//P2SEL1 = 0;
//SYSCFG2 |= USCIBRMP;
//#endif

// TODO: To verify the SMCLK, enable its output on pin P1.1
//P1SEL1 = (BIT0);


PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings

// Configure USCI_B0 for I2C mode
UCB0CTLW0 |= UCSWRST; // put eUSCI_B in reset state
UCB0CTLW0 |= UCMODE_3 | UCMST; // I2C master mode, SMCLK
UCB0BRW = 5 ; // baudrate = SMCLK / 5 = 400Khz
UCB0TBCNT = 0x0003; //number of bytes to be received (NEW)
UCB0I2CSA = 0x33; // configure slave address
UCB0CTLW0 &=~ UCSWRST; // clear reset register
UCB0IE |= UCTXIE0 | UCNACKIE; // transmit and NACK interrupt enable


__enable_interrupt();



//TASK BEGIN

while(RXData != 0x0F)
{
//243243245 = ~30s
__delay_cycles(24324324); // Delay between transmissions
TXByteCtr = DataLength; // Load TX byte counter
while (UCB0CTLW0 & UCTXSTP); // Ensure stop condition got sent
UCB0CTLW0 |= UCTR | UCTXSTT; // I2C TX, start condition
__bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
// Remain in LPM0 until all data
// is TX'd

//Make sure that UCB0CTLW0 is interchangeable with UCB0CTL1
while(RXData != 0x0F)
    {
    __delay_cycles(2000);
    while (UCB0CTL1 & UCTXSTP);         // Ensure stop condition got sent
    UCB0CTL1 |= UCTXSTT;                // I2C start condition

    __bis_SR_register(LPM0_bits|GIE);   // Enter LPM0 w/ interrupt


    if(RXData == 0x0F)
    //if(1)
    {
        P1OUT ^= BIT0;                      // Toggle P1.0 using exclusive-OR
    }
    else
    {
        __delay_cycles(200000); // Delay between transmissions
        TXByteCtr = DataLength; // Load TX byte counter
        while (UCB0CTLW0 & UCTXSTP); // Ensure stop condition got sent
        UCB0CTLW0 |= UCTR | UCTXSTT; // I2C TX, start condition
        __bis_SR_register(LPM0_bits | GIE); // Enter LPM0 w/ interrupts
    }

    }

}

}



//TASK END










#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCIB0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCIB0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,USCI_I2C_UCBIT9IFG))
{
case USCI_NONE: break; // Vector 0: No interrupts break;
case USCI_I2C_UCALIFG: break;
case USCI_I2C_UCNACKIFG:
UCB0CTL1 |= UCTXSTT; //resend start if NACK
break; // Vector 4: NACKIFG break;
case USCI_I2C_UCSTTIFG: break; // Vector 6: STTIFG break;
case USCI_I2C_UCSTPIFG: break; // Vector 8: STPIFG break;
case USCI_I2C_UCRXIFG3: break; // Vector 10: RXIFG3 break;
case USCI_I2C_UCTXIFG3: break; // Vector 14: TXIFG3 break;
case USCI_I2C_UCRXIFG2: break; // Vector 16: RXIFG2 break;
case USCI_I2C_UCTXIFG2: break; // Vector 18: TXIFG2 break;
case USCI_I2C_UCRXIFG1: break; // Vector 20: RXIFG1 break;
case USCI_I2C_UCTXIFG1: break; // Vector 22: TXIFG1 break;
case USCI_I2C_UCRXIFG0: break; // Vector 24: RXIFG0 break;
case USCI_I2C_UCTXIFG0:
if (TXByteCtr) // Check TX byte counter
{
UCB0TXBUF = TXData[0]; // Load TX buffer
TXByteCtr--; // Decrement TX byte counter
}
else
{
UCB0CTLW0 |= UCTXSTP; // I2C stop condition
UCB0IFG &= ~UCTXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0
}
break; // Vector 26: TXIFG0 break;
case USCI_I2C_UCBCNTIFG: break; // Vector 28: BCNTIFG
case USCI_I2C_UCCLTOIFG: break; // Vector 30: clock low timeout
case USCI_I2C_UCBIT9IFG: break; // Vector 32: 9th bit
default: break;
}
}