CCS/MSP432P401R: MSP432P401R SPI Slave Code

/* Setting DCO to 12MHz */
    CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);

void EUSCIB0_IRQHandler(void)
{
    uint32_t status;

    P1OUT |= BIT0;
#if 1
    if (EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)
    {
        receiveData[receiveDataCount++] = EUSCI_B0->RXBUF;
    }

#else
    status = SPI_getEnabledInterruptStatus(EUSCI_B0_BASE);
    SPI_clearInterruptFlag(EUSCI_B0_BASE, status);

    if(status & EUSCI_B_SPI_RECEIVE_INTERRUPT)
    {
        //Receive data from master
        receiveData[receiveDataCount++] = SPI_receiveData(EUSCI_B0_BASE);
    }
#endif

    if (receiveDataCount == receiveDataCmdLength)
    {
        receiveDataCount = 0;
    }
    P1OUT &= ~BIT0;
}

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/*******************************************************************************
 * MSP432 SPI - 3-wire Slave Incremented Data
 *
 * SPI slave talks to SPI master using 3-wire mode. Data is received
 * from master and data from slave is then transmitted back to master.
 * USCI RX ISR is used to handle communication, CPU normally in LPM0.
 * Prior to initial data exchange, master pulses slaves RST for complete
 * reset.
 *
 * Note that in this example, EUSCIB0 is used for the SPI port. If the user
 * wants to use EUSCIA for SPI operation, they are able to with the same APIs
 * with the EUSCI_AX parameters.
 *
 * Use with the master version of the code example
 *
 *                MSP432P401
 *              -----------------
 *             |                 |
 *             |                 |
 *             |                 |
 *             |             P1.6|<- Data In (UCB0SIMO)
 *             |                 |
 *             |             P1.7|-> Data Out (UCB0SOMI)
 *             |                 |
 *             |             P1.5|<- Serial Clock In (UCB0CLK)
 *
*******************************************************************************/
/* DriverLib Includes */
#include <ti/devices/msp432p4xx/driverlib/driverlib.h>
#define RECEIVE 0
#define TRANSMIT 1

/* Statics */
//static volatile uint8_t transmitData = 0x01, receiveData = 0x00;
static volatile uint8_t state = RECEIVE;
static volatile uint8_t transmitDataCount = 0x00;
static volatile uint8_t transmitDataInit[2] = {0xD5,0xE5};
static volatile uint8_t receiveData[2] = {0,0};
static volatile uint8_t receiveDataCount = 0x00;
static volatile uint8_t receiveDataCmdLength = 0x02;
static volatile uint16_t receiveDataCmd = 0x5678;

/* SPI Slave Configuration Parameter */
const eUSCI_SPI_SlaveConfig spiSlaveConfig =
{
        EUSCI_B_SPI_MSB_FIRST,                          // MSB First
        EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT,  // Phase
        EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW,     // Normal Polarity
        EUSCI_B_SPI_3PIN                               // 3wire mode
};

int main(void)
{
    /* Stop watchdog timer */
    WDT_A_holdTimer();

    /* Setting DCO to 24MHz */
    CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24);

    /* Selecting P1.5 P1.6 and P1.7 in SPI mode */
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
            GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_PRIMARY_MODULE_FUNCTION);

    /* Initialize slave to MSB first, inactive high clock polarity and
     * 3 wire SPI */
    SPI_initSlave(EUSCI_B0_BASE, &spiSlaveConfig);

    /* Enable the SPI module */
    SPI_enableModule(EUSCI_B0_BASE);

    /* Enable Receive interrupt */
    SPI_enableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_RECEIVE_INTERRUPT);
    /* Disable Transmit interrupt */
    SPI_disableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT);
    Interrupt_enableSleepOnIsrExit();
    Interrupt_enableInterrupt(INT_EUSCIB0);

    Interrupt_enableMaster();
    PCM_gotoLPM0();

}

void EUSCIB0_IRQHandler(void)
{
    uint32_t status;

    P1OUT |= BIT0;
#if 1


    if (EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG0)
    {
        receiveData[receiveDataCount++] = EUSCI_B0->RXBUF;
    }
    else if(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG0)
    {
        /* USCI_B0 TX buffer ready? */
        while (!(SPI_getInterruptStatus(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT)));

        // Transmit data to master
        SPI_transmitData(EUSCI_B0_BASE, transmitDataInit[transmitDataCount]);
        transmitDataCount++;
        if (transmitDataCount >= 2)
        {
            transmitDataCount = 0;
            SPI_disableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT);    // Disable Transmit interrupt
            SPI_enableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_RECEIVE_INTERRUPT);      // Enable Receive Interrupt
        }
    }

#else
    status = SPI_getEnabledInterruptStatus(EUSCI_B0_BASE);
    SPI_clearInterruptFlag(EUSCI_B0_BASE, status);

    if(status & EUSCI_B_SPI_RECEIVE_INTERRUPT)
    {
        //Receive data from master
        receiveData[receiveDataCount++] = SPI_receiveData(EUSCI_B0_BASE);
    }
#endif

    if (receiveDataCount == receiveDataCmdLength)
    {
        receiveDataCount = 0;
        // USCI_B0 TX buffer ready?
        while (!(SPI_getInterruptStatus(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT)));

        // Transmit data to master
        SPI_transmitData(EUSCI_B0_BASE, transmitDataInit[transmitDataCount]);
        transmitDataCount++;

        // Enable Transmit interrupt
        SPI_enableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT);

        // Disable Receive interrupt
        SPI_disableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_RECEIVE_INTERRUPT);

    }
    P1OUT &= ~BIT0;
}