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If a falling edge is sent from the external M-Bus master to the TSS721A, the voltage on pin PF (pin 5) will break down to 1.4 V for about 5 μs. This voltage in turn causes an interrupt routine to be triggered in our microcontroller in order to process the supposed power fail. The output voltage of the TSS721A and all other voltages are in the normal range. Since this effect occurs at each falling edge of the normal received signal, the effect is very disturbing.
In the meantime I have found a work-around by supporting the signal PF with a capacitor and the voltage drop is correspondingly reduced.
What I'm interested in is an explanation of why this PF break-in comes, and what TI's approach recommends. In the datasheet of the TSS721A no indication can be found. All the exemplary circuits are designed without a capacitor, and this effect is nowhere mentioned.
I have attached a screenshot of measurements with the oscilloscope showing the M-Bus voltage (yellow) and the PF_N signal (green).
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