MSP430FR5989: Decoupling Guidance

Hello,

That's a good observation. To explain the difference, keep in mind that the external reference fed into VeREF+/- would be an input that's used to reference several modules in the MSP430. Thus, it'd be important to have a stable, noise-free signal which is why we recommend decoupling capacitors in the datasheet. Now, when using the internal reference as an output on VREF+/-, this would be an output rather than an input. Let's assume you're referencing an external ADC module with VREF+/-. You wouldn't put decoupling capacitors near the VREF+/- output pins of the MSP430 but rather near the reference input pins of the external ADC module. Why? Because additional noise gets picked up between the signal output and signal input.

In summary, decoupling is typically used near inputs rather than outputs.

Regards,

James

msp430fr5989-ep_Apr2017.pdf

Hi James,

I was not specific enough.  Table 4-34 lists built-in characteristics of the voltage reference.  below is an excerpt from said table.

Is this a characteristic of this pin P1.1 for VREF+ or is it a limitation of external capacitance?  The internal ADC draws the same 200uA no matter if the if the internal reference is used or an external reference is used.  So what is the meaning of this?  Is VREF+ unstable above 100pF?  if so that would seem like a useless VREF+.   Can you please clarify this?  Is the internal reference actually decoupled at AVCC?

If you use the pin as a reference output, any capacitance is not  decoupling but is loading down the opamp buffer. Opamps as a rule do not care for a capacitive load. If you need to drive more than 100pF (why?) you should add a buffer designed to drive that load.

I am seeking to understand what this multifunction pin P1.1 really is when configured as VREF+.  You are saying it is an opamp buffer. 

How do you know this?  I have not found an explicit schematic.   There is very little clear guidance in using the internal ADC with the internal reference.  Plenty with an external reference. 

I need to be sure when the internal ADC S/H circuit takes its gulp of current that the internal reference is not going to drop more than 1.2mV (2LSBs).  Proper decoupling will be a 10uF (3.9uF allowing for voltage drop in an X7R at 2.5V bias)

That's why I asked also "Is the internal reference actually decoupled at AVCC?"

Hi Carl,

Carl Brooks said:

I am seeking to understand what this multifunction pin P1.1 really is when configured as VREF+.  You are saying it is an opamp buffer. 

How do you know this?  I have not found an explicit schematic.   There is very little clear guidance in using the internal ADC with the internal reference.  Plenty with an external reference. 

David may be referring to the REF_A block diagram in Figure 33-1 in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide. There, it shows what appears to be op-amps used as buffers.

Carl Brooks said:

I need to be sure when the internal ADC S/H circuit takes its gulp of current that the internal reference is not going to drop more than 1.2mV (2LSBs).  Proper decoupling will be a 10uF (3.9uF allowing for voltage drop in an X7R at 2.5V bias)

I'm asking our internal teams for more clarity on the external capacitance range. It may be a few days or more than a week before I can get any information, so thanks for your patience. Looking at other external references (e.g. TL4051A), there's a certain load capacitance range that can cause them to become unstable. There's a lower and upper range for acceptable loading capacitance, and the region in-between should be avoided. I'm assuming that our MSP430FR5989 datasheet is specifying the lower range for the decoupling capacitance and the upper range isn't available or wasn't characterized. I may not be able to confirm that but I'm trying to find out more.

Carl Brooks said:

That's why I asked also "Is the internal reference actually decoupled at AVCC?"

Table 5-34 indicates that REF_A is supplied by AVCC, and since that connection is internal, I'm assuming the decoupling capacitors at the AVCC pin(s) help filter out noise from the power supply before it enters the REF_A module.

Regards,

James

The diagram for VREF shows that the ADC has a local buffer. The ADC diagram shows a buffer. The values for ADC12VRSEL only provide for VREF buffered. (You can select VeREF buffered or unbuffered.) It is a pretty safe bet that this buffer is an opamp.

The data sheet shows the ADC specifications using both the internal and external reference. (It is better with an external reference.) You can be certain that performance using the internal reference will meet those specifications so long as you don't load REFOUT excessively. Which means limiting the current drawn and the parasitic capacitance. 100pF being a capacitance consistent with parasitics rather than a part you add. Note also that the ADC specifications when using the internal reference do not indicate that REFOUT was enabled.

The S/H pulls that big gulp of current from your signal source, not VREF. VREF only comes into play once the conversion starts.