CCS/MSP430FR5994: Memory write (FRAM) issue

Retokid

Part Number: MSP430FR5994
Other Parts Discussed in Thread: MSP-EXP430FR5994

Tool/software: Code Composer Studio

I'm in the process of migrating our firmware code to a MSP430FR5994 micro controller, everything was going rather fine until I activated the main clock with an external 16MHz quartz.

After searching for a day or two, the issue boils down to this problem : when I activate an SMCLK divider, writing to FRAM doesn't happen any more.

I've written a small piece of code (attached below) to illustrate the problem:

initialize whatever is absolutely necessary, set the master clock at 16Mhz, without an SMCLK divider,
write to FRAM,
clear the FRAM.

The result can easily be checked by displaying the (info) memory area at 0x1800, and so far this works as a charm. However, if I step further:

set a SMCLK divider,
write to FRAM,
clear the FRAM.

Nothing is written to FRAM.

I have tried this on two MSP-EXP430FR5994 boards with consistent results.

If I replace the DIVS__2 with DIVM__2, everything is OK.

I have found no indication on such a (known) bug...

So, what's happening here ?

#include <msp430.h> 

#include <stdint.h>

/**
 * main.c
 */

void test()
{
    uint8_t i;

    for (i=0; i < 255; i++)
        *((uint8_t *)0x1800 + i) = i;
}

void clear()
{
    uint8_t j;

   for (j=0; j < 255; j++)
       *((uint8_t *)0x1800 + j) = 0xff;
}

int main(void)
{
    CSCTL0 = CSKEY;
    CSCTL1 = DCORSEL | DCOFSEL_4;

    test();
    clear();

    CSCTL3 = DIVM__2;

    test();
    clear();

    return 0;
}

over 5 years ago

0 Retokid over 5 years ago

Intellectual 580 points

So the code I posted is the working version with DIVM__2, with DIVS__2 this will not work.

0 David Schultz over 5 years ago

Guru 22955 points

Maximum clock speed without wait states (see FRAM controller) is 8MHz.

0 Retokid over 5 years ago in reply to David Schultz

Intellectual 580 points

So ? It works at 16Mhz, not at 8Mhz, quite the contrary of what you seem to suggest.

0 David Schultz over 5 years ago in reply to Retokid

Guru 22955 points

Let me be more clear. Maximum MCLK is 8Mhz without wait states. You say it works with DIVM_2 and that is why.

0 Retokid over 5 years ago in reply to David Schultz

Intellectual 580 points

It works with or without DIVM at any frequency, it does not work with any DIVS (neither /2 nor /4). And by the way I can't see why it would not work if the frequency involves wait states.

0 Retokid over 5 years ago in reply to Retokid

Intellectual 580 points

Well, indeed at 8Mhz, it works with or without DIVS.

So the issue seems to be related with a clock frequency > 8Mhz and a DMCLK divider, still can't see why.

0 David Schultz over 5 years ago in reply to Retokid

Guru 22955 points

The maximum MCLK frequency is clearly stated in the data sheet and the family guide covers operation of the FRAM controller in detail. This is not a mystery.

0 Retokid over 5 years ago in reply to David Schultz

Intellectual 580 points

Sorry but I can't get see your point.

My issue is with SMCLK, not with MCKL. Furthermore it works perfectly well at 16Mhz. So I simply can't relate what you say to my issue, can you clarify ?

0 Bruce McKenney over 5 years ago

Guru 96285 points

> CSCTL3 = DIVS__2; // (per text)

This sets DIVM=0, which runs MCLK=16MHz, which (as David pointed out) is too fast with NWAITS=0. I suggest you set a breakpoint at the second line of main() to see if the CPU is reset-ing.

I also don't see where you stop the Watchdog. That could be interfering with your test. That breakpoint will also catch the reset if it happens.

0 Retokid over 5 years ago in reply to Retokid

Intellectual 580 points

So, why this works at 16Mhz DCO without wait states and no MCLK divider is mystery, but off-specs, why it doesn't work anymore with a SMCLK divider is even more unclear. Simply adding a wait state with :

FRCTL0 = FRCTLPW | NWAITS_1;

fixes the issue.

I wasn't aware the wait states need to be set manualy, thanks to David helping.

0 Bruce McKenney over 5 years ago in reply to Retokid

Guru 96285 points

DIVM=3 (/8) at reset, so everything was fine until you set DIVM=0. [Ref User Guide (SLAU367O) Table 3-7]

0 Retokid over 5 years ago in reply to Bruce McKenney

Intellectual 580 points

,-) Yep that's a clear explanation.

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CCS/MSP430FR5994: Memory write (FRAM) issue