Hi team,
Our customer is looking for SPI-to-I2C bridge device. Since it does not seem TI have this bridge chip, we will plan to introduce MSP430FR2310.
Connection structure is, "External CPU---> [SPI/Slave : MSP430 :I2C/Master] -->ROM"
this means, MSP430’s SPI is “Slave”, MSP430’s I2C is “Master”.
Would you think that customer is able to do this implementation? Is there any concern for this implementation?
MSP430FR2310 is supporting I2C 400KHz, however, I’m not sure this device is supporting max of Serial clock for SPI, Could you elaborate it, please? My concern is buffer-overflow at this time.
Best regards,
Miyazaki