MSP430I2041: Problem with lack of noise immunity in impulse noise testing

Hello,

Let me check with our team members with more ESD experience.

Regards,

James

O.H,

were you able to review the PCB with respect to supply loops as mentioned in "MSP430 System-Level ESD Considerations", on page #17 and #18. It is essential to keep the loop inductance of the supply as low as possible to minimize impact to the chip itself.
Also I would recommend to focus on any traces on the PCB which represents a big capacitance (long routed signals, signals connected to connectors or pin headers) and also GPIO pins which might create loops on the PCB where a magnetic field can couple in.

For the loops I recommend to minimize loop inductance by reducing loop size or implementing a serial resistor (some ohm) close the pin preventing the residual pulse from EFT event propagating into the device. Same is true for the electric field attacking the signals which represents a big capacitance but a serial resistor close to the device pin to block the fast residual pulse. Final these so called System Efficient ESD Design concept is also described on page #22 in the above linked document.

Pls let me know if this helps.

Hi Dietmar Walther,

Thank you for your quick reply.

Dietmar Walther said:

were you able to review the PCB with respect to supply loops as mentioned in "MSP430 System-Level ESD Considerations", on page #17 and #18. It is essential to keep the loop inductance of the supply as low as possible to minimize impact to the chip itself.
Also I would recommend to focus on any traces on the PCB which represents a big capacitance (long routed signals, signals connected to connectors or pin headers) and also GPIO pins which might create loops on the PCB where a magnetic field can couple in.

For the loops I recommend to minimize loop inductance by reducing loop size or implementing a serial resistor (some ohm) close the pin preventing the residual pulse from EFT event propagating into the device. Same is true for the electric field attacking the signals which represents a big capacitance but a serial resistor close to the device pin to block the fast residual pulse. Final these so called System Efficient ESD Design concept is also described on page #22 in the above linked document.

I will pass on the advice you gave to my customers.

I'm sorry, could you please answer an additional question?

Is it possible to use the TEST pin shorted to GND?
→We have confirmed that open is the recommended treatment for unused pins. Also, we understand that shorting the TEST pin to GND will make it impossible to write. As one of the ESD countermeasures, let me check if there is no problem in device operation even if the test pin is directly shorted to GND after writing the program.

Is there any software (or hardware) countermeasure for DCO in MSP430I20xx?

We will share additional information from our customers as soon as we have it.

Best regards,
O.H

O.H

the TEST pin is required for JTAG access either 4 wire JTAG or SBW where acts as CLK pin. So if the application does not require on board JTAG access after programming short it to GND can be done. However ensure the grounding happens close to the TEST pin to not generate an inductive loop. Also good to know is that TEST pin has internal a pull down so grounding it will not have an effect to functional behavior except the impact to JTAG explained before.

For the DCO you have the capability to P1.0 and P1.1 via SMLCK or MCLK if you do not observe after testing on these pins it has multiple reason e.g. device went through reset,....

So what I recommend is to do a dynamic current measurement before EFT testing to record the current profile of the application over a defined time frame. Once EFT is done unit is in the dedicated mode you describe another dynamic IDD measurement can give some glue what the device is doing and if still operating. Also it can give indications to latch-up scenarios. Most easy thing is to apply a simple GPIO port toggle test to observe the functionality before, during and after EFT testing.

Hi Dietmar Walther,

Thank you for your reply.

I understood about the TEST pin.

Dietmar Walther said:

For the DCO you have the capability to P1.0 and P1.1 via SMLCK or MCLK if you do not observe after testing on these pins it has multiple reason e.g. device went through reset,....

This is the first one to be checked. The customer implemented a simple code to output MCLK from P1.0 and SMCLK from P1.1. When using the internal DCO as the clock source, the outputs of MCLK and SMCLK could not be confirmed after applying noise. At this time, MSP430 was not reset even though a signal changing from Low to High was input to the RST/NMI pin. When using an external crystal oscillator as clock source, reset by RST/NMI pin was possible.

Dietmar Walther said:

So what I recommend is to do a dynamic current measurement before EFT testing to record the current profile of the application over a defined time frame. Once EFT is done unit is in the dedicated mode you describe another dynamic IDD measurement can give some glue what the device is doing and if still operating. Also it can give indications to latch-up scenarios. Most easy thing is to apply a simple GPIO port toggle test to observe the functionality before, during and after EFT testing.

Sorry about that. I didn't understand the meaning of "IDD" and "Glue" here. So I did not understand the purpose of checking the dynamic current of the application before applying noise. What can I learn about DCO by looking into this? Does it lead to a solution that does not use an external crystal oscillator?

In case you are wondering, the customer is using a 7 Segment LED, and the LED was on before the noise was applied, but after the noise was applied, the LED was off whether the DCO was used or the external crystal oscillator was used. Also, when they switched the external crystal oscillator, which originally had a 5V output (divided and output 3.3V), directly to a 3.3V output, for some reason the noise immunity dropped by about 100V.

O.H said:

Q2: Comparing MSP430F4270 and MSP430I2041, is there any difference in noise immunity?
We have done the same test with MSP430F4270 and it passed without any problem, so we would like to see if there is any difference as a device just in case.

Can you please answer this question again?
The customer had created a similar application using MSP430F4270 in the past. However, the customer is looking for a reason why the difference between F4270 and I2041 is too large, since F4270 passes the test with voltages up to plus 2500V without following the "MSP430 System ESD Troubleshooting Guide". Is there a difference in noise immunity at the IC level between the I2041 and the F4270?

Also, I think the F4270 has a dedicated pin for JTAG (4-wire). However, in the I2041, the pin is also used for other functions, so is it likely to be affected by noise?

Best regards,
O.H

O.H

thanks for additional information,looks like the DCO stops and RST pin functionality disappeared correct?
So if the external crystal oscillator was used the clock stops as well but the RST pin stays functional, is this understanding correct?

The item on IDD measurement is to see how the current consumption of the device changes e.g. from some 100uA in normal operation to either several mA or maybe some single uA.

Regarding the LED comment: Not sure how the 7 segment LED is controlled by the I2040 most probably via PWM so looks like whole chip goes into some kind of stuck mode.

The differences between i2040 and F4270 are huge. They are coming from different process nodes and also are completely different in architecture so concluding from changes to EFT performance is not really possible. As you might see System Level ESD or EFT aspects are not covered by the datasheet which are mainly covering HBM/CDM (unpowered ESD to cover manufacturing process under ESD controlled conditions).
The point on System Level is the big impact from PCB and other external components that's why TI cannot provide SOC specific noise thresholds and that is why the above mentioned documents were published. So if a customer application should have these System Level requirements the recommendations from the Apps Notes should be followed to pass these kind of tests.

As said again supply loops, other inductive loops and large capacitances on the board play a significant role.

Hi Dietmar Walther,

Thanks for the reply.

Dietmar Walther said:

thanks for additional information,looks like the DCO stops and RST pin functionality disappeared correct?
So if the external crystal oscillator was used the clock stops as well but the RST pin stays functional, is this understanding correct?

Yes, You are right. Strictly speaking, when using the external crystal oscillator, we have not confirmed that the CLK from P1.0 and P1.1 is stopped, but the system is outputting Timer pulses from P2.7, and these pulses seem to be stopped. (As a result, the external WDT is no longer receiving the pulse output and is issuing a reset signal.)

We have asked the customer to check the difference in current consumption of Idd(=power supply current?) before and after applying noise. It may take some time to investigate as they will be making changes to the board.

Dietmar Walther said:

Regarding the LED comment: Not sure how the 7 segment LED is controlled by the I2040 most probably via PWM so looks like whole chip goes into some kind of stuck mode.

It is controlled by GPIO high/low. This is a slightly special control method that uses a CMOS decoder to control 8-digit segments with 3 digits due to insufficient number of pins.

Dietmar Walther said:

The differences between i2040 and F4270 are huge. They are coming from different process nodes and also are completely different in architecture so concluding from changes to EFT performance is not really possible. As you might see System Level ESD or EFT aspects are not covered by the datasheet which are mainly covering HBM/CDM (unpowered ESD to cover manufacturing process under ESD controlled conditions).
The point on System Level is the big impact from PCB and other external components that's why TI cannot provide SOC specific noise thresholds and that is why the above mentioned documents were published. So if a customer application should have these System Level requirements the recommendations from the Apps Notes should be followed to pass these kind of tests.

As said again supply loops, other inductive loops and large capacitances on the board play a significant role.

Thanks for your insights. The customer himself could understand to some extent about the point where the difference happens at the system level. First of all, I would like to go and check the difference between the board with MSP430F4270.

Best regards,
O.H

Hi Dietmar Walther.

Thank you too for the additional advice and quick support.

I will focus on Vcore and ROSC and continue my research. If we have any additional results, we will create another thread, and we would appreciate your help at that time.

Beset regards,
O.H