TM4C1292 ncpdt-Ethernet.

Hello,

Hello,

The 50 mhz rmii clock is toggling fine.

Gpiopinconfigure(pm4),This function i used properly before sysctrl peripheral enable.

I am using tiva ware example libraries,Actually now we are trying MAC-MAC communication between Ethernet switch and Micro controller.

So weather i have to use phy enable and phy initialization.

The code is getting halted in EMAC RESET function,while loop.

How to proceed please provide an answer.

Regards,

Krishnan

Krishnan G Nair said:

How to proceed please provide an answer.

 Hi, please don't use this form of sentence, instead gently ask volunteer in community if someone can help forever in a good manner, this is imperative form and hurt people, we are not at your service.

Krishnan G Nair said:

The code is getting halted in EMAC RESET function,while loop.

 Before do emac reset are all register of MAC and PHY correctly loaded, MAC unit to uC in particular, are they?

Krishnan G Nair said:

I am using tiva ware example libraries,Actually now we are trying MAC-MAC communication between Ethernet switch and Micro controller.

 Please can you post PHY and MAC register you loaded to Micrel device?

Hi Krishnan,

>EMAC_BCONFIG_MIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED, 32, 32, 0);//4,4

Something gut tells me this line is where EMAC has a fit and MPU halts, do not believe it is proper to combine mixed burst with priority fixed.

Umm perhaps try fixed burst. Datasheet discussion DMA arbitration states with mixed burst we also set a priority weight and ratio.

Hello,

Thank you for the information, i got now the EMACRESET issue resolved.But  i can't send data from controller to pc via switch.

I am using RMII interface via switch and Controller.Actually switch is not configured right now as default configurations itself is enough to communicate.

I am attaching my code also any suggestions please ...

Regards,

Krishnan

Hi KGN,

> i got now the EMACRESET issue resolved

How about sharing your find?

Still stand firm it is not proper to have mixed priority DMA arbitration with a fixed burst rate, seemingly for reasons given in the text.

> Ethernet Mac of controller to Micreal switch(MAC) using RMII Interface.

Not sure why you what to have External PHY communicate to switch MAC/MAC. Don't they do that normally when forming a MAC frame on the device layer?

Perhaps you are describing  the switch port is configured 802.1q trunk port to support VLANS? If so it stands to reason you must also configure the EMAC for 802.1q VLAN frame schema.

BTW: TTC/RTC are Ignored when (TX/RX(StoreFwd)[21,25] are set.

Example of DMA priority burst ratio:

/* Initialize the MAC setting the DMA mode Rx/Tx Bursts size words.
 * Set Transmit priority weight 2, Burst priority ratio 2:1.
 * EMACInit() must be called after any calls to EMACPHYConfigset().
 * REG57:0xC00 (EMACDMABUSMOD) */

 MAP_EMACInit(EMAC0_BASE, ui32SysClkHz,
//EMAC_BCONFIG_FIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED |
  EMAC_BCONFIG_TX_PRIORITY | EMAC_BCONFIG_MIXED_BURST |
  EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 | EMAC_BCONFIG_PRIORITY_2_1,
			 8, 8, 0);

Hi KGN,

See your TM4c1292ncpdt requires to add the external PHY chip just the opposite TM4C1294 where the PHY is built in.

Do the interrupts need to be enabled for the external PHY and possibly consider to set an INT priority for the MAC?

  ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT);
  EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val);

HI KGN,

Appears a few other issues  in the code you posted. Seems you started to configure the RMII PHY clock source then never finished.

RMII clock enable source is not set (internal / external) and the TMP MAC address (01,02,03,01,02,03) may be consider invalid MAC by the switch.

Typical code:

    //
    // If using an external RMII PHY, we must set 2 bits in the Ethernet MAC
    // Clock Configuration Register.
    //
        //
        // Select and enable the external clock from the RMII PHY.
        //
        HWREG(EMAC0_BASE + EMAC_O_CC) |= EMAC_CC_CLKEN;

Hello,

How we resolved the EMACReset(EMAC0_BASE); Halt  Issue is 

1)Configuration Done on RMII Signals

GPIOPinConfigure(GPIO_PG3_EN0TXEN);
GPIOPinConfigure(GPIO_PG5_EN0TXD1);
GPIOPinConfigure(GPIO_PG4_EN0TXD0);
GPIOPinConfigure(GPIO_PG7_EN0RXDV);
GPIOPinConfigure(GPIO_PQ5_EN0RXD0);
GPIOPinConfigure(GPIO_PQ6_EN0RXD1);
GPIOPinConfigure(GPIO_PK4_EN0INTRN);
GPIOPinConfigure(GPIO_PF2_EN0MDC);
GPIOPinConfigure(GPIO_PF3_EN0MDIO);
GPIOPinConfigure(GPIO_PM4_EN0RREF_CLK);

2)Our TIVA_RMII_50MHZ-was unstable so we made a pull down and made it stable.

Regarding Emac -Switch Interface problem still exist.

3)Link LED is blinking when connecting External PHY AND PC.

4)In TM4C1292NCPDT DATASHEET  (pAGE nO:1452 20.4 Initialization and Configuration) for RMII 

EMACReset(EMAC0_BASE);
HWREG(EMAC0_BASE + EMAC_O_CC) |= (EMAC_CC_CLKEN|EMAC_CC_PTPCEN);
HWREG(EMAC0_BASE +EMAC_O_DMABUSMOD) |=(EMAC_DMABUSMOD_SWR);

I have  done the above configuration and according to forum members suggestions i made changes the Mixed Burst and PHY interrupts.

Still the result the same.

I am attaching my project folder alsoCTI_NPOL_NWG.rar

Hi All

Can you please help to clarify my below doubts ?

1. If I use RMII mode, the tiva datasheet listed to enable ECEXT and CLKEN bit in the EMACCC register.
I can find CLKEN bit , but ECEXT bit is not listed in the datasheet

2. Tiva datasheet says Select the RMII interface by programming the PINTFS bit field to 0x4 in EMACPC register
but that register is stated as ReadOnly.. What is the bit position of PINTFS

3. EMACPHYREAD & EMACPHYWRITE - These API's can be used to read the External PHY registers also ?
or these API's are meant for only internal PHY inside Tiva

Please help me on the above

Thanks in advance
Krishnan

Hello,

Thank you for the replay.

>1.I tried with broadcast MAC address(FF-FF-FF-FF-FF-FF) and braodcast ip(This i tested successfully for TM4C1294 UDP program(RAW SOCKET-NOT LWIP OR UIP).

One more doubt I am having is  

>2.what is the difference EMAC PHY WRITE and EMAC EXTENDED PHYWRITE?

Looking forward for suggestions.

Thanks in advance.

Regards,

Krishnan

So it seems the hardware PHY confirmed working by the UDP test and the TCP or other configuration aspect remains suspect?

For the TM4c1294NCPDT:

Extend write gains access to program the PHY registers via the address provided to (MII Management (Accessed through the EMACMIIADDR Register)).

Like this:

    // Using the EMAC0 MII address field in REG5 0x10 to configure PHY MR37 (EPHYLEDCFG)
    // and reconfigure TX/RX activity for LED2, Flash 5Hz datasheet pages 1486, 1638, 1647
    // EMAC_PHY_PK4LED0LNK_PK5LED2ACTY or EMAC_PHY_PF0LED0LNK_PF1LED2ACTY
    MAP_EMACPHYExtendedWrite(EMAC0_BASE, EMAC_MIIADDR_PLA_M, EPHY_LEDCFG, EMAC_PHY_PF0LED0LNK_PF4LED1ACTY);

    MAP_EMACPHYExtendedWrite(EMAC0_BASE, EMAC_MIIADDR_PLA_M, EPHY_LEDCR, EPHY_LEDCR_BLINKRATE_5HZ);

Hello,

I managed the issues at that time itswlf.

Use external Rmii phy configurations for controller to initialise phy

Remaining things are like usual procedure.

Any more further doubts just mail me .it is as simple.

Regards,

Krishnan