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Hello,
We are looking to use the DRV8300 in a non-standard circuit configuration; specifically we are looking to swap the high-side and low-side outputs such that the low-side output goes to the gate of a P-channel FET on the high side of the motor phase output, due to the fact that only the low-side inputs are invertible. That would mean that the high-side output is now being used to toggle the low-side gate, so a boost cap should no longer be necessary (what seemed to be a possible issue with this ticket: https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1090986/drv8300-3phase-mosfet-driver)
We were wondering though whether this might cause issues with the DRV8300 internally though, or if you guys had any other advice.
Thank you for your assistance!
Hi Amaresh,
Thank you for posting to the Motor Drivers forum!
The bootstrap (BSTx) capacitor is necessary as it helps to maintain the bootstrap voltage above the under-voltage lockout for normal operation. This is important because if the bootstrap voltage falls below the value shown below (which can be found in the electrical characteristics table of the datasheet), a system shutdown could be triggered.
More information on the bootstrap under-voltage lockout can be found in Section 8.3.3.1 VBSTx Undervoltage Lockout (BSTUV) of the datasheet.
Best,
~Alicia
Hi Alicia,
From my understanding, the bootstrap is only necessary when using dual N-FETs for the actual high- and low-side phase drivers, correct? My apologies, but we are looking to use the DRV8300 with a different phase driver architecture, specifically using a P-FET for the high-side driver, and an N-FET only for the low-side driver. Because of this, I think a bootstrap voltage is no longer necessary, as the gate of the high-side P-FET only needs to swing between 0V and the motor power rail.
The issue though is that we must then invert the control signal going to the high side control input pins. We were thinking that, rather than inverting the signal in our motor control firmware, we could instead use the MODE pin and invert the low side control input pins, and swap to using the "low side" control pins for the high side P-FET gates in our topology instead. The "high side" pins would then control the actual low side N-FETs in our topology, and so would not need the boost voltage rail as the low side N-FETs sources' stay at 0V.
Please let me know if this is still confusing, I can put up a rough schematic of what I am thinking of.
Regards,
Amaresh
Hi Amaresh,
If you could provide a schematic showcasing what you are describing, that would be great.
Also, something to keep in mind, the DRV8300 is protected against BSTx under-voltage, refer to section 8.3.3 Gate Driver Protective Circuits of the datasheet for more detailed information. To summarize, if there is ever a point where the voltage on one of the BSTx pins falls below the VBSTUV threshold, the high side external MOSFET of that phase will be disabled by disabling the GHx pins until the BSTx under-voltage condition is cleared. Therefore, in order to maintain the bootstrap voltage above the under-voltage lockout, an appropriately sized bootstrap capacitor must be chosen.
Best,
~Alicia
Hi Alicia,
Here is a schematic snippet showing how we are planning on using the DRV8300:
To get over the boost undervoltage lockout, we are grounding all the source feedback pins, and also bypassing the internal boost diode as it is not necessary with the P-FETs being on the high side. I believe this should allow any voltage rail above the Vbstuv max threshold to be used, as long as there is enough local capacitance to keep the motor power rail stable at higher switching frequencies. There are some additional details/notes in the schematic snippet but please let me know if you need any more info.
Regards,
Amaresh
Hi Amaresh,
Thank you for sharing the schematic. I will aim to provide some feedback before the end of next week.
Best,
~Alicia
Hi Amaresh,
Thank you for your patience.
While it would be possible to forgo the bootstrap capacitor if you are using a P-FET on the high side of the gate driver, it is not recommended as the device was designed with the intention of being used with 2 N-FETs.
To help me further understand, what would be the benefit of using the P-FET in combination with the N-FET instead of using 2 N-FETs?
Best,
~Alicia