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UCC28070A: Parts damaged

Zhonghui Xu
Expert 5445 points
Part Number: UCC28070A

Hi team,

I help my customer to ask a question.

"

We have a test jig for UCC28070A chips, to check we haven’t accidentally ESD damaged them.

Please advise on this test jig for UCC28070A….please may I ask if its OK?

We have the UCC28070A set up for 0.9 Max duty cycle. We apply Vcc = 12V. We then, via separate resistive dividers, put a test voltage of 2V into each of the VINACP and VSENSE pins.

Do you agree, this should result in Current and voltage error amplifiers being railed high, (CAOA and VOA railed high) and the gate drive outputting 0.9?

We are only using the “A” stage. So we have the CAOB pin grounded.

"

Thank you very much for your help.

Best regards,

  • 0
    TI__Mastermind 23315 points

    Hi Zhonghui,

    Thank you for the query. 

    What is connected to CSA input and IMO pin? It will be easier to understand if you can provide a rough hand sketch of the test setup.

    Regards,

    harish

  • 0 in reply to Harish Ramakrishnan5
    TI__Expert 5445 points

    Hi harish,

    Thank you for your help.

    The attached shows the setup. There is no mains attached for this test, just the 12V bias voltage input to the UCC28070A.
    The Multiplier pin (IMO) just has a resistance to ground connected to it.
    CSA pin has the Burden resistor of the Current sense transformer connected to it, and also the reset network of the current sense transformer...however, there is no signal from the current sense transformer as there is no mains for this test.

    UCC28070A on test.pdf

    Best regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23315 points

    Hi Zhonghui,

    Thank you for the clarification. Firstly applying direct DC voltage to Vinac is going to be an issue as kvff won't be updated due to lack of zero crossings, so IMO reference to the current sense amplifiers might not be accuate. VAO will be high (depending on the voltage amplifier gain and the difference of the 3V and the applied 2V signal ) as you suggested, but output of the CAO will depend on the referece current from IMO and CSA pin input adn this is going to be compared with the pWM ramp to generate the required duty at gate output. I am not sure if it will result in a directly translation of 0.9 duty pulse at the ouput. This has to be verified on bench/simulated but the idea seems to be ok. What signal will be you be forcing into the the CSA pin?

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    TI__Expert 5445 points

    Hi Harish,

    Thankyou so much Harish,
    I will be putting no signal into the CSA pin.....so  as you know, it'll just be pulled to ground by the burden resistor there.
    To be honest, i dont mind if it  doesnt give the set 0.9 Duty cycle, but we just want to see the gate drive pulsing, so we can tell, to an extent, that we havent accidentally ESD damaged the chip.
    Many thanks.

    Best regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23315 points

    Hi Zhonghui,

    Thank you for the reply.

    From what I understand, if CSx is GNDed, the IMO voltage (for that phase) will always be higher than the corresponding Outx, so CAx will try to drive an output current.  The transconductance gain is 100uA/V but CAx has a current limit of 50uA. If CAx is grounded, the set input is high, so the Qbar output is low and the DRV will be low. In the first case, we should be seeing a gate output with high duty cycle ( but might not be 0.9) . Please let me know your observations and if you have any questions.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    TI__Expert 5445 points

    Hi Harish,

    Thank you so much for your help.
    When  we did this test, our UCC28070A was giving an irregular gate drive output,  it was giving a train of gate pulses, then nothing, then a train of pulses again, etc etc. The duty cycle of the gate pulses, when it gave them, was sometimes 0.9, but sometimes would be about 0.05. Then sometimes  it would "scroll" from min to max duty cycle.
    As such, we assumed that we must have accidentally ESD  Damaged the UCC28070A. Would you agree with this?

    Best regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23315 points

    Hi Zhonghui,

    Thank you for the reply.

    When the synthesized current coming from the CS pin is above the IMO reference, the CAO output will be low and the duty cycle will be close to zero or a low value. In your case when the CS pin is held close to GND (or low value), CAO output will be driven high and the gate pulse should have a constant higher duty cycle given the static conditions. I would recommend checking with another sample also. Probably the current sample is not functioning properly. Please let me know your observations.

    Regards,

    Harish

  • 0 in reply to Harish Ramakrishnan5
    TI__Expert 5445 points

    Hi Harish,

    Thank you so much for your help.
    Customer feedback: the problem was resolved.
    Thanks again.

    Best regards,

  • 0 in reply to Zhonghui Xu
    TI__Mastermind 23315 points

    Hi Zhonghui,

    Thank you for the reply. Glad to know it was resolved.

    Regards,

    Harish