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TPS650864: Control interface waveform question.

Part Number: TPS650864
Other Parts Discussed in Thread: CSD87381P, TIDA-01393,

Dear Guys,

         It was found that 3 control signals (GPO1/3/4) are different from the normal ones. Normally they keep in always 1V.

Tommy.

TI TPS6508641RSKR PMIC question.pptx

  • Hi Tommy,

    Looking at Table 8-6 in the datasheet, it shows GPO2 is configured as a low state by default. For the ones configured as open-drain, a pull-up resistor is needed to the desired high voltage level. Does this explain what you are observing?

    Best regards,

    Matt

  • Dear Matt:

             I add the detail information in attach file.


    TI TPS6508641RSKR PMIC question_20240122_0A.pptx

    Tommy

  • Hi Tommy,

    GPO1, GPO3, and GPO4 are power good signals for the TPS6508641:

    • GPO1 does not need a pull-up resistor since it is a push-pull configured pin. GPO1 will be HIGH when BUCK1 reaches Power good status and CTL3 is HIGH.
    • GPO3 will only become HI-Z (pulled- up to 3.3V through resistor) when BUCK4 reaches power good status and CTL1 is pulled HIGH (there is a 50ms delay after the final condition is met for GPO3 to go HIGH)
    • GPO4 will only become HI-Z (pulled-up to 3.3V through resistor) when BUCK4 reaches power good status and CTL5 is pulled HIGH

    If the GPOx signals are switching between HIGH and LOW rapidly that would indicate some issue with the power sequence or the pull-up supply voltage.

    Regards,

    James

  • Hi Tommy,

    Please make sure you are looking at the power up sequence Figure 8-11 in the datasheet for my below comments.

    From Page 4:

    1. You may remove R386 on GPO1 since this pin is push-pull configured
      1. Why is CTL3 only rising to 1.2V if you are using the LDO 3.3V pull-up source? The timing of CTL3 should follow LDO3P3 ramp up.
    2. The power sequence looks correct but there are some scope signals that aren't shown.
      1. CTL3 is pulled-up to LDO3P3 so I would expect CTL3 to ramp up slightly before BUCK1 since BUCK1 must wait for LDO5P0 gate driver to reach full function.
      2. GPO1 ramps up slightly after BUCK1 reaches power good so this is expected

    From Page 5:

    1. BUCK4 does not appear to be reaching a stable power good status. Please read registers 0xB2 through 0xB6 to check for any power fault indications (bits set to 1'b).
    2. CTL1 is connected to LDP3V3 but is only pulled up to 1.2V which doesn't seem to make sense to me. I would recommend pulling CTLx signals up to 1.8V or 3.3V to ensure a clear HIGH signal for the CTLx input. The full power up sequence depends on each BUCK reaching power good status. If BUCK4 is not reaching power good the sequence will not continue
      1. CTL1 rise time can be anywhere in the power sequence so it doesn't matter where in the sequence CTL1 becomes HIGH. CTL1 should only be tied to GPO3
      2. GPO3 does not reach HIGH status because BUCK4 is not reaching power good status
      3. The power sequence show on slide 5 does not appear to match the sequence in Figure 8-11 from the datasheet.

    From Page 6:

    1. BUCK4 is still resetting in this scope capture. GPO4 is showing square waveform because GPO4 ramps up soon after BUCK4 and BUCK5 so there is a small period of time where GPO4 registers the power good of BUCK4 and BUCK5. Once the BUCKs reset, the GPO4 signal goes low again and the cycle repeats. Also CTL5 is 1.2V but in the schematic the pin is pulled-up to 3.3V LDO so I am confused about this measurement.
    2. The power sequence shown on slide 6 is not the same as the power sequence in Figure 8-11. CTL4 should come at the beginning of the power sequence to begin the power up.
      1. CTL5 is an input signal controlled by your design. If you have CTL5 pulled-up to LDO3V3, the signal will become HIGH before BUCK4 ramps up. The CTLx signals can be pulled HIGH at any time in the sequence since the BUCKs are also controlled by power good signal of previous rails.
      2. GPO4 is controlled by power good of BUCK4 and CTL5 HIGH to enable. In the scope capture, GPO4 is pulled HIGH every time BUCK4 reaches the target regulation voltage which is the expected behavior. The repeated start of BUCK4 is not expected. BUCK4 should ramp up and remain stable.

    Please double check the power up sequence using Figure 8-11 in the datasheet. Note that  Figure 8-11 has one error - LDOA1 should ramp up after BUCK4 power good is reached. This is the only correction to remember for Figure 8-11. All the other rails should show the correct sequence.

    In order to figure out why BUCK4 is having issues, double check that all requirements are met in the TPS65086x Schematic and Layout Checklist (Rev. A)

    Regards,

    James

  • Hi Tommy,

    From Slide 5:

    • The repeated reset behavior in the waveforms indicates that the PMIC is experiencing a power fault during the power up sequence. If a fault occurs, a status bit is latched in registers 0xB2 through 0xB6 to indicate which rail is experiencing the fault.
    • In order to read these registers you need a host device that can use I2C communication. The SCL and SDA pins on the TPS6508641 need to be pulled up to 3.3V or 1.8V for I2C communication to work.

    From Slide 6:

    • Correction: I was looking at the wrong table for the GPO1 configurations. GPO1 is open-drain configuration for TPS6508641 so you will need R386 for pull-up source. I will show the correct table below:


    • CTL3 is a user controlled signal. The rise time of CTL3 will depend on the pull-up supply source. Since CTL3 is pulled up to LDO3P3, CTL3 will rise sooner than BUCK1. BUCK1 ramps up after LDO3P3 and LDO5P0 in the power sequence. The CTLx signals are marked in red on the power sequence because the user has control over when these signals ramp up to HIGH state.

    From Slide 7:

    • Reading registers requires I2C communication from the host device. Reading the I2C while the IC is on your board would require you to either use the host processor or break into the I2C lines using a separate tool.

    • The differences in the power sequence between different document versions are due to changes on Xilinx side. When they alter their processor system, the PMIC must change the power sequence to accommodate the new power up requirements.

    From Slide 8:

    • BUCK4 is one of the rails that is showing the power fault reset issue but it may not be the source of the power fault. A power fault on one rail causes all rails to reset because the power sequence starts over from the beginning. It actually looks like BUCK4 ramps up to the target voltage for a bit before each reset occurs. This means that the power fault may be happening further into the power sequence so it is important to check all rails to see which rail fails to reach the target regulation point.

    From Slide 9:

    • The programming of these ICs should be the same as far as I know. Usually this can be verified by doing a full register dump and comparing the data to a sample chip. However, it sounds like you don not currently have the capability to check the registers.
    • From what I can tell from you scope captures it looks like the power sequence is trying to follow the datasheet spec but there is a physical fault stopping the power up process. I don't think there is an issue with the sequence programming from a software perspective.

    Can you share the full schematic as a PDF so I can take a look? If you need to share the file privately I can set up a private message space.

    Regards,

    James

  • Dear Matt:

             update

    Tommy

  • Hi Tommy,

    Based on the new slides concerning BUCK6 it should be noted that TPS6508641 is a preprogrammed PMIC version so BUCK6 will be active by default after every power cycle (BUCK6 is tied to CTL4 with the other BUCKs).

    Even if you don't plan on using BUCK6 in your system, you need to provide the passive components as if the rail will be used because the PMIC is still monitoring the BUCK6 output. You should not be connecting SW6 or FBVOUT6 to GND since BUCK6 will be active. You will need to supply all the proper components for switching activity. The output capacitance can be low if you aren't planning to load the BUCK6 rail but you need a bit of output capacitance for stability.

    It looks like you're getting an overcurrent fault which would make sense if you are connecting BUCK6 output directly to GND or to low impedance.

    Regards,

    James

  • Dear James:

            Please check page4 and 5

    TI TPS6508641RSKR PMIC question with TI_20240201_0A.pptx

    Tommy

  • Hi Tommy,

    • Yes, if BUCK6 is enabled you will need the FETs, inductor, and output capacitors to support switch regulation. The PMIC will be looking for the correct BUCK6 FB for the power up sequence.
       
      You can disable BUCK6 using register 0x27 bit 0 = 0'b but you will need to do this after every power cycle before the power sequence reaches BUCK6, otherwise you will trigger a fault without passive components. If you can use I2C to disable BUCK6 before starting the power sequence, then you could avoid using BUCK6 components.

    I'm not sure what is causing the power fault. I see that you have many scope shots shared but the power rails are not all shown in order from start to finish so it's difficult to piece together the device behavior. Please provide the below information so we can better debug this issue:

    1. Please fill out the following schematic checklist and share your full schematic for the board you are testing: TPS65086x Schematic and Layout Checklist (Rev. A).
      1. Mark each item as "Used (or Not Used) & Complete in the column on the right. Once the checklist is done, share the completed document as well as the schematic.
      2. I'm not talking about the block diagram for the processor connection. I need the schematic for the PMIC pin connections and components. If you need to share it privately we can set up a space for you to send the files directly to me.
         
    2. Please take the following scope shots:
      1. Scope shot showing VSYS, LDO5P0, LDO3P3, and CTL4 over time (use 2ms per division on the oscilloscope to make sure these signals remain stable for the full power sequence)
         
      2. Scope shot showing CTL4, BUCK1, BUCK2, and BUCK5 over time (use 2ms per division on the oscilloscope to make sure these signals remain stable for the full power sequence)
         
      3. Scope shot showing BUCK2, BUCK6, and GPO1 over time (use 2ms per division on the oscilloscope to make sure these signals remain stable for the full power sequence)
         
        The goal of the scope captures is to identify the first error that appears in the power sequence. As soon as you identify which power rail is the first to show an issue in the sequence, you need to check for any other rails that show issues at that moment. Sometimes, the first rail to show an issue is actually responding to a rail later in the sequence. By matching the timing of different power faults, you can narrow down which rail is the source of the problem.

    Regards,

    James

  • Hi Tommy,

    I need the full schematic to double check these checklist items.

    Regards,

    James

  • Hi Tommy,

    Thank you for sending the schematic. I will take a look and provide an update within 2 business days.

    Regards,

    James

  • Hi Tommy,

    I only have a couple notes about the schematic:

    Regards,

    James

  • Dear James:

             1. What is the relative relationship or formula between R388 and VCC_PSAUX? exp: What is the voltage of VCC_PSAUX when R388 is 2.37KOhm? What is the voltage of VCC_PSAUX when R388 is 10KOhm?

            2. The datasheet tps650864-SWCS138E.pdf page50 mentions "If RILIM is too low for the chosen inductor and voltage conditions, then the ripple current at no load will trigger the negative current limit, forcing the low side FET to turn off. This will eventually result in the output voltage increasing above target regulation point due to irregular duty cycle created by current limit being triggered." -- So, there will be no problem of increasing voltage if there is a load?

               Because the board we bought online (with Xilinx CPU) also uses 2.37K but does not have the problem of excessive Buck6 voltage (6~8V). Could it be that after completing the boot sequence, some commands are issued to the PMIC through I2C? Can Buck6 voltage always maintain the 1.8V we want?

    Tommy

  • Hi Tommy,

    The device expert is currently out of the office. They will look into this and provide a response when they return. Please expect some delay accordingly.

    Thanks,
    Field

  • add two point.

    4. Which of the following combinations will have a normal Buck6 voltage?

        a. R388 is 2.37Kohm and L22 is 0.22uH

        b. R388 is at least 4.5k and L22 is 0.22uH

        c. R388 is 2.37Kohm and L22 is 2.2uH

        d. R388 is at least 4.5k and L22 is 2.2uH

    5. Are Buck1 and 2 OK?

    Tommy

  • Hi Tommy,

    1. R388 does not control the VCC_PSAUX output voltage. The output voltage is set by the respective register value and R388 sets the current limit for that power rail.
       
      Calculating the correct RILIM is done using equations 1 and 2 from the datasheet (page 50). You can also use equations 3 and 4 on the same page if you plan to use Forced PWM mode. In this way, RILIM depends on the VOUT voltage but the actual voltage set point is not determined by the ILIM resistor.
       
    2. If there is a load applied to the output, then you no longer have negative inductor current so the issue described at the bottom of page 50 wouldn't apply anymore. The LSFET turning off is a result of the negative inductor current reaching the limit.
       
    3. BUCK6 should be able to maintain the 1.8V target but you may want to confirm the RILIM resistor value using the equations I mentioned above. If you have a working example board that can power up with the 2.37kOhm resistor, then there might be something else causing the shutdown. If you have a working board I would suggest comparing the two schematics to see where your design is different. If everything is the same between the two boards there might be an issue with one of the external components.
       
    4. I would suggest either combination B or D in order to make sure RILIM for BUCK6 isn't too low. I'm basing this suggestion on that other E2E thread I linked where this solved the startup issue for a customer.
       
      For the inductor value, you need to follow equation 5 on page 110 of the datasheet in order to figure out what inductor value is recommended. Generally, I think the 2.2uH inductor value is more common in the designs I see but it depends on your ripple and current targets.

    Regards,

    James

  • Dear James:

            R388 does not control the VCC_PSAUX output voltage. The output voltage is set by the respective register value and R388 sets the current limit for that power rail.

            [Tommy]Which register?

    Tommy

  • What values ​​should I enter for the parameters in equations 1 and 2? 

    RDSON?

    VIN = 12V?

    Vout = 1.8V?

    ILIM?

    Iripple?

    ILIMREF = 50uA?

    Lmax = 0.22uH?

    fsw?

  • Hi Tommy,

    Output voltage control for BUCK6 is in R98[7:1].

    For RDSON I would use the max value from the CSD87381P datasheet, which would be 8.4mΩ

    VIN would be 12V

    Vout would be 1.8V

    ILIM would be your target current limit that you want to achieve

    Iripple is the minimum peak-to-peak inductor ripple current for a given VOUT.

    For ILIMREF you can use the typical value of 50uA

    Lmax would be the max expected inductance so if your inductor has a tolerance window, I would use the higher end of the spectrum (slightly larger inductance value). You can also decide whether temperature has any affect or not.

    fsw for the buck controllers is typically 1MHz but I would add some margin on this for the max fsw value and use 1.2MHz.

    To be clear, these equations can help optimize the RILIM resistor but if you are only testing with small load currents you may want to simply try a 5k or 7k resistor just to see if the low resistance is the cause of your issue.

    Also swapping to a higher inductor would be worth checking. I usually see at least 0.47uH on this rail so you can try any value from 0.47uH to 2.2uH to see if that helps.

    Regards,

    James

  • Dear James:

            SO, RDSON isn’t you want to read the following?

             Please detail review our schematic again whether OK? include RLC value. I will update to E2E simultaneously.

             Change component: R388, L22, C690, C695, C696, C732, C734, C692

              Add component: C2200 to C2208

    AUV6 FPGA_20240301_0A_TI.pdf

    Tommy

  • Dear James:

           We found the reference schematic for XILINX XCZU2CG from the TI official website (TIDA-01393 reference design | TI.com). Should we use this one as a reference?

    Tommy
  • Hi Tommy,

    The RDSON you shared is for the Gate Driver FETs, not the LSFET. You should use the LSFET RDSON since this FET is part of the voltage regulator power path.

    The schematic changes look good. I will be interested to see if this solves the power up issue. If the power up issue persists we can try some other avenues of debugging. 

    The Xilinx reference design you mentioned (TIDA-01393) can be used as a guide. One thing I noticed is that the TIDA reference design uses 1.18kΩ for the ILIM6 pin which is even lower than your original resistor value. If the schematic changes you made end up fixing the power up issue you may be able to experiment with lowering the ILIM resistance back to your original target but I'm still concerned that having ILIM too low can cause issues with BUCK6 regulation.

    For now I would keep RILIM at a higher value until we are sure that the problem is coming from somewhere else in on the board.

    Regards,

    James

  • Dear James:

    OK! We will use this version of AUV6 FPGA_20240301_0A_TI.pdf to design the new version of PCB. In addition, can we provide the layout (Allegro version)? Can you help us see if there is anything that needs to be improved? Can you also help us with PDN simulation?

    Tommy
  • Dear James:

             We have compared some differences. Can you help us confirm what else needs to be modified?

    1. The FB resistance value of Buck1 (is there a calculation formula for reference)?

    2. Buck2 does not require FB resistor value?

    3. Is the inductance of Buck2 larger than 0.47uH?

    The difference between AUV6 and TI_Tommy.xlsx

    Tommy

  • Dear James:

             Modify the number of Buck1 to Buck6 output capacitors between AUV6 FPGA_20240304_0A_TI.pdf and AUV6 FPGA_20240301_0A_TI.pdf

    AUV6 FPGA_20240304_0A_TI.pdf

    Tommy

  • HI Tommy,

    I can take a look at the layout if you provide the design files.

    The only simulation file we have is the Flotherm model which is located on the TPS650864 product page. We don't have a PSPICE model for this part to use in a full PDN simulation.

    For he FB network of BUCK1, use a 294k and 25.5k resistor. The FBVOUT1 pin is looking for 0.4V when BUCK1 is set for 5V output.

    BUCK2 should not have any resistor dividers on the FBVOUT2 pin.

    The inductor value of BUCK2 can be optimized with the equation I mentioned above (same for BUCK1 and BUCK6). 0.47uH is usually the smallest inductor value that I see for this BUCK. You can also try 1uH or 2.2uH depending on your DC current and ripple current targets.

    Regards,

    James

  • Dear James:

             you mean: we need to change our schematic?

             1. We need change Buck1 FB resister from 390K and 33.2K to 294k and 25.5k resistor? What is the value of FBVOUT for 390K and 33.2K?

             2. Buck2 haven't FB resister? the same Buck6?

    Tommy

  • Dear James:

             This is layout file, please help me to check. Thanks!

    AUV6_GA-718_V0_pmic.brd

    Tommy

  • Dear James:

             The only simulation file we have is the Flotherm model which is located on the TPS650864 product page. We don't have a PSPICE model for this part to use in a full PDN simulation. -- You mean is Flotherm model is only simulation PMIC itself and PSPICE model can simulation PMIC schematic? or can use other simulation tool(exp:ADC.....etc) import our layout file simulation?  

    Tommy

  • Hi Tommy,

    I'll take a look at the layout and let you know my feedback within 2 business days.

     you mean: we need to change our schematic?

             1. We need change Buck1 FB resister from 390K and 33.2K to 294k and 25.5k resistor? What is the value of FBVOUT for 390K and 33.2K?

             2. Buck2 haven't FB resister? the same Buck6?

    As long as the ratio of the resistors gives you 0.4V on FBVOUT1, you should be fine. I don't think you have to change the resistor values.

    BUCK2 and BUCK6 do not need FB resistors at all. Just connect the FB pin to the positive side of the output capacitors.

    You mean is Flotherm model is only simulation PMIC itself and PSPICE model can simulation PMIC schematic? or can use other simulation tool(exp:ADC.....etc) import our layout file simulation?  

    A PSPICE simulation would be able to take into account the external components and simulate the PMIC outputs. The Flotherm model is only for PMIC temperature simulation and I'm not as familiar with this model type.

    All I'm saying is that we don't have a PSPICE model to provide for the TPS650864. I don't believe we have any models of this part besides the Flotherm model.

    Regards.

    James

  • Hi Tommy,

    I took a look at the layout and I don't see any issues with the pin connections.

    There were only a couple notes I made:

    • C694 doesn't appear to be placed on the layout. I looked it up using a search function and the component didn't have a location on the x-y grid.
    • For the VTT output pours, it looks like GND and PS_AVCC are overlapping. That might not be how the board is actually constructed but I wanted to mention it in case this is not intentional.

    Regards,

    James

  • Dear James:

             1. Sorry, I didn't capture the location of C694. The following relevant locations are for your reference. Should we put C694 close to the PMIC? And it is on the same layer.

             2. Are you talking about the white box in the picture below?

                  It should be that the setting has gone away. The correct one is as follows

      Tommy
  • Dear James:

             Can R381 and R382 be maintained in our current design first, because there is a reserved resistor position, and then maybe R382 can be replaced with 0Ohm and R381 is not installed to achieve the FB pin to the positive side of the output capacitors. The same Buck6.

    Tommy

  • Dear James:

             Could you help me to double check layout list whether meet your requirement?

    6470.TPS650860 Schematic Checklist Layout Checklist for Compal_0205_Hank.xlsx

    Tommy

  • Dear James:

             1. For CSD87381P, there are 9 through holes in the pink frame, 2 of which are on PGND and the other 7 are around PGND, right? If we have a VIA with layer1 to layer2 (GND), can we do this without drilling a through hole? We must do you want to fight so much?

           2. For TPS6508641RSKR, please give us some suggestions for the following files.

    AUV6 PMIC layout check_20240304_0B.xlsx

    Tommy

  • Hi Tommy,

    It should be that the setting has gone away. The correct one is as follows

    Thank you for clarifying those first notes about the layout, I think the new pour for VTT output looks good now.

       Can R381 and R382 be maintained in our current design first, because there is a reserved resistor position, and then maybe R382 can be replaced with 0Ohm and R381 is not installed to achieve the FB pin to the positive side of the output capacitors. The same Buck6.

    Yes, you can replace R382 with a 0Ohm resistor and remove R381.

     Could you help me to double check layout list whether meet your requirement?
    • For FBGND2, if possible I would recommend routing the trace over to the GND side of the output capacitors for better regulation accuracy.
    • Input capacitor GND should be as close as possible to FET GND to maintain a small power loop. What you have currently should be fine.
    For CSD87381P, there are 9 through holes in the pink frame, 2 of which are on PGND and the other 7 are around PGND, right? If we have a VIA with layer1 to layer2 (GND), can we do this without drilling a through hole? We must do you want to fight so much?

    I'm not sure what you mean by this question. Adding an array of thermal vias can help dissipate thermal energy into the GND plane of the PCB so I would recommend adding these vias as shown by the layout guide. For more information I would make a separate post about the CSD87381P since I am less familiar with this specific FET.

    For TPS6508641RSKR, please give us some suggestions for the following files.
    • For #4: The FB trace you have should be fine. It's not unusual to have longer FB traces when targeting the point of load for example.
    • For #7: The routing you currently have should work. You can optimize the driver loops by following the layout advice but the improvements may not be worth the effort of redesigning the routing.

    For further debug, I would still like to see a full power sequence captured on an oscilloscope with the power rails in order and lined up to show the timing. On another thread, I captured the TPS6508641 power up sequence. I will paste the results below. This is the behavior you should be looking for during power up.

    Regards,

    James

  • Dear James:

             Please review and check layout again. Thanks!

    AUV6_GA-718_V0A_pmic0308.brd

    Tommy

  • Hi Tommy,

    I have already reviewed the layout so if the changes are in line with the feedback, there's no reason to review the full file again. Please let me know when you have further test data of the IC behavior directly.

    Regards,

    James