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Dear Guys,
It was found that 3 control signals (GPO1/3/4) are different from the normal ones. Normally they keep in always 1V.
Tommy.
Hi Tommy,
Looking at Table 8-6 in the datasheet, it shows GPO2 is configured as a low state by default. For the ones configured as open-drain, a pull-up resistor is needed to the desired high voltage level. Does this explain what you are observing?
Best regards,
Matt
Dear Matt:
I add the detail information in attach file.
TI TPS6508641RSKR PMIC question_20240122_0A.pptx
Tommy
Hi Tommy,
GPO1, GPO3, and GPO4 are power good signals for the TPS6508641:
If the GPOx signals are switching between HIGH and LOW rapidly that would indicate some issue with the power sequence or the pull-up supply voltage.
Regards,
James
Hi Tommy,
Please make sure you are looking at the power up sequence Figure 8-11 in the datasheet for my below comments.
From Page 4:
From Page 5:
From Page 6:
Please double check the power up sequence using Figure 8-11 in the datasheet. Note that Figure 8-11 has one error - LDOA1 should ramp up after BUCK4 power good is reached. This is the only correction to remember for Figure 8-11. All the other rails should show the correct sequence.
In order to figure out why BUCK4 is having issues, double check that all requirements are met in the TPS65086x Schematic and Layout Checklist (Rev. A).
Regards,
James
Hi Tommy,
From Slide 5:
From Slide 6:
From Slide 7:
From Slide 8:
From Slide 9:
Can you share the full schematic as a PDF so I can take a look? If you need to share the file privately I can set up a private message space.
Regards,
James
Hi Tommy,
Based on the new slides concerning BUCK6 it should be noted that TPS6508641 is a preprogrammed PMIC version so BUCK6 will be active by default after every power cycle (BUCK6 is tied to CTL4 with the other BUCKs).
Even if you don't plan on using BUCK6 in your system, you need to provide the passive components as if the rail will be used because the PMIC is still monitoring the BUCK6 output. You should not be connecting SW6 or FBVOUT6 to GND since BUCK6 will be active. You will need to supply all the proper components for switching activity. The output capacitance can be low if you aren't planning to load the BUCK6 rail but you need a bit of output capacitance for stability.
It looks like you're getting an overcurrent fault which would make sense if you are connecting BUCK6 output directly to GND or to low impedance.
Regards,
James
Hi Tommy,
I'm not sure what is causing the power fault. I see that you have many scope shots shared but the power rails are not all shown in order from start to finish so it's difficult to piece together the device behavior. Please provide the below information so we can better debug this issue:
Regards,
James
Hi Tommy,
I need the full schematic to double check these checklist items.
Regards,
James
Hi Tommy,
Thank you for sending the schematic. I will take a look and provide an update within 2 business days.
Regards,
James
Hi Tommy,
I only have a couple notes about the schematic:
Regards,
James
Dear James:
1. What is the relative relationship or formula between R388 and VCC_PSAUX? exp: What is the voltage of VCC_PSAUX when R388 is 2.37KOhm? What is the voltage of VCC_PSAUX when R388 is 10KOhm?
2. The datasheet tps650864-SWCS138E.pdf page50 mentions "If RILIM is too low for the chosen inductor and voltage conditions, then the ripple current at no load will trigger the negative current limit, forcing the low side FET to turn off. This will eventually result in the output voltage increasing above target regulation point due to irregular duty cycle created by current limit being triggered." -- So, there will be no problem of increasing voltage if there is a load?
Because the board we bought online (with Xilinx CPU) also uses 2.37K but does not have the problem of excessive Buck6 voltage (6~8V). Could it be that after completing the boot sequence, some commands are issued to the PMIC through I2C? Can Buck6 voltage always maintain the 1.8V we want?
Tommy
Hi Tommy,
The device expert is currently out of the office. They will look into this and provide a response when they return. Please expect some delay accordingly.
Thanks,
Field
add two point.
4. Which of the following combinations will have a normal Buck6 voltage?
a. R388 is 2.37Kohm and L22 is 0.22uH
b. R388 is at least 4.5k and L22 is 0.22uH
c. R388 is 2.37Kohm and L22 is 2.2uH
d. R388 is at least 4.5k and L22 is 2.2uH
5. Are Buck1 and 2 OK?
Tommy
Hi Tommy,
Regards,
James
Dear James:
R388 does not control the VCC_PSAUX output voltage. The output voltage is set by the respective register value and R388 sets the current limit for that power rail.
[Tommy]Which register?
Tommy
What values should I enter for the parameters in equations 1 and 2?
RDSON?
VIN = 12V?
Vout = 1.8V?
ILIM?
Iripple?
ILIMREF = 50uA?
Lmax = 0.22uH?
fsw?
Hi Tommy,
Output voltage control for BUCK6 is in R98[7:1].
For RDSON I would use the max value from the CSD87381P datasheet, which would be 8.4mΩ
VIN would be 12V
Vout would be 1.8V
ILIM would be your target current limit that you want to achieve
Iripple is the minimum peak-to-peak inductor ripple current for a given VOUT.
For ILIMREF you can use the typical value of 50uA
Lmax would be the max expected inductance so if your inductor has a tolerance window, I would use the higher end of the spectrum (slightly larger inductance value). You can also decide whether temperature has any affect or not.
fsw for the buck controllers is typically 1MHz but I would add some margin on this for the max fsw value and use 1.2MHz.
To be clear, these equations can help optimize the RILIM resistor but if you are only testing with small load currents you may want to simply try a 5k or 7k resistor just to see if the low resistance is the cause of your issue.
Also swapping to a higher inductor would be worth checking. I usually see at least 0.47uH on this rail so you can try any value from 0.47uH to 2.2uH to see if that helps.
Regards,
James
Dear James:
SO, RDSON isn’t you want to read the following?
Please detail review our schematic again whether OK? include RLC value. I will update to E2E simultaneously.
Change component: R388, L22, C690, C695, C696, C732, C734, C692
Add component: C2200 to C2208
Tommy
Dear James:
We found the reference schematic for XILINX XCZU2CG from the TI official website (TIDA-01393 reference design | TI.com). Should we use this one as a reference?
Hi Tommy,
The RDSON you shared is for the Gate Driver FETs, not the LSFET. You should use the LSFET RDSON since this FET is part of the voltage regulator power path.
The schematic changes look good. I will be interested to see if this solves the power up issue. If the power up issue persists we can try some other avenues of debugging.
The Xilinx reference design you mentioned (TIDA-01393) can be used as a guide. One thing I noticed is that the TIDA reference design uses 1.18kΩ for the ILIM6 pin which is even lower than your original resistor value. If the schematic changes you made end up fixing the power up issue you may be able to experiment with lowering the ILIM resistance back to your original target but I'm still concerned that having ILIM too low can cause issues with BUCK6 regulation.
For now I would keep RILIM at a higher value until we are sure that the problem is coming from somewhere else in on the board.
Regards,
James
Dear James:
OK! We will use this version of AUV6 FPGA_20240301_0A_TI.pdf to design the new version of PCB. In addition, can we provide the layout (Allegro version)? Can you help us see if there is anything that needs to be improved? Can you also help us with PDN simulation?
Dear James:
We have compared some differences. Can you help us confirm what else needs to be modified?
1. The FB resistance value of Buck1 (is there a calculation formula for reference)?
2. Buck2 does not require FB resistor value?
3. Is the inductance of Buck2 larger than 0.47uH?
The difference between AUV6 and TI_Tommy.xlsx
Tommy
Dear James:
Modify the number of Buck1 to Buck6 output capacitors between AUV6 FPGA_20240304_0A_TI.pdf and AUV6 FPGA_20240301_0A_TI.pdf
Tommy
HI Tommy,
I can take a look at the layout if you provide the design files.
The only simulation file we have is the Flotherm model which is located on the TPS650864 product page. We don't have a PSPICE model for this part to use in a full PDN simulation.
For he FB network of BUCK1, use a 294k and 25.5k resistor. The FBVOUT1 pin is looking for 0.4V when BUCK1 is set for 5V output.
BUCK2 should not have any resistor dividers on the FBVOUT2 pin.
The inductor value of BUCK2 can be optimized with the equation I mentioned above (same for BUCK1 and BUCK6). 0.47uH is usually the smallest inductor value that I see for this BUCK. You can also try 1uH or 2.2uH depending on your DC current and ripple current targets.
Regards,
James
Dear James:
you mean: we need to change our schematic?
1. We need change Buck1 FB resister from 390K and 33.2K to 294k and 25.5k resistor? What is the value of FBVOUT for 390K and 33.2K?
2. Buck2 haven't FB resister? the same Buck6?
Tommy
Dear James:
The only simulation file we have is the Flotherm model which is located on the TPS650864 product page. We don't have a PSPICE model for this part to use in a full PDN simulation. -- You mean is Flotherm model is only simulation PMIC itself and PSPICE model can simulation PMIC schematic? or can use other simulation tool(exp:ADC.....etc) import our layout file simulation?
Tommy
Hi Tommy,
I'll take a look at the layout and let you know my feedback within 2 business days.
you mean: we need to change our schematic?
1. We need change Buck1 FB resister from 390K and 33.2K to 294k and 25.5k resistor? What is the value of FBVOUT for 390K and 33.2K?
2. Buck2 haven't FB resister? the same Buck6?
As long as the ratio of the resistors gives you 0.4V on FBVOUT1, you should be fine. I don't think you have to change the resistor values.
BUCK2 and BUCK6 do not need FB resistors at all. Just connect the FB pin to the positive side of the output capacitors.
You mean is Flotherm model is only simulation PMIC itself and PSPICE model can simulation PMIC schematic? or can use other simulation tool(exp:ADC.....etc) import our layout file simulation?
A PSPICE simulation would be able to take into account the external components and simulate the PMIC outputs. The Flotherm model is only for PMIC temperature simulation and I'm not as familiar with this model type.
All I'm saying is that we don't have a PSPICE model to provide for the TPS650864. I don't believe we have any models of this part besides the Flotherm model.
Regards.
James
Hi Tommy,
I took a look at the layout and I don't see any issues with the pin connections.
There were only a couple notes I made:
Regards,
James
Dear James:
1. Sorry, I didn't capture the location of C694. The following relevant locations are for your reference. Should we put C694 close to the PMIC? And it is on the same layer.
2. Are you talking about the white box in the picture below?
It should be that the setting has gone away. The correct one is as follows
Dear James:
Can R381 and R382 be maintained in our current design first, because there is a reserved resistor position, and then maybe R382 can be replaced with 0Ohm and R381 is not installed to achieve the FB pin to the positive side of the output capacitors. The same Buck6.
Tommy
Dear James:
Could you help me to double check layout list whether meet your requirement?
6470.TPS650860 Schematic Checklist Layout Checklist for Compal_0205_Hank.xlsx
Tommy
Dear James:
1. For CSD87381P, there are 9 through holes in the pink frame, 2 of which are on PGND and the other 7 are around PGND, right? If we have a VIA with layer1 to layer2 (GND), can we do this without drilling a through hole? We must do you want to fight so much?
2. For TPS6508641RSKR, please give us some suggestions for the following files.
AUV6 PMIC layout check_20240304_0B.xlsx
Tommy
Hi Tommy,
It should be that the setting has gone away. The correct one is as follows
Thank you for clarifying those first notes about the layout, I think the new pour for VTT output looks good now.
Can R381 and R382 be maintained in our current design first, because there is a reserved resistor position, and then maybe R382 can be replaced with 0Ohm and R381 is not installed to achieve the FB pin to the positive side of the output capacitors. The same Buck6.
Yes, you can replace R382 with a 0Ohm resistor and remove R381.
Could you help me to double check layout list whether meet your requirement?
For CSD87381P, there are 9 through holes in the pink frame, 2 of which are on PGND and the other 7 are around PGND, right? If we have a VIA with layer1 to layer2 (GND), can we do this without drilling a through hole? We must do you want to fight so much?
I'm not sure what you mean by this question. Adding an array of thermal vias can help dissipate thermal energy into the GND plane of the PCB so I would recommend adding these vias as shown by the layout guide. For more information I would make a separate post about the CSD87381P since I am less familiar with this specific FET.
For TPS6508641RSKR, please give us some suggestions for the following files.
For further debug, I would still like to see a full power sequence captured on an oscilloscope with the power rails in order and lined up to show the timing. On another thread, I captured the TPS6508641 power up sequence. I will paste the results below. This is the behavior you should be looking for during power up.
Regards,
James
Hi Tommy,
I have already reviewed the layout so if the changes are in line with the feedback, there's no reason to review the full file again. Please let me know when you have further test data of the IC behavior directly.
Regards,
James