LM5148: LM5148

Hello Sanjana,

Part of the problem is you are laying this out on a two-layer board, so you don't have a solid ground plane.  As such the distances you have are creating undesirable parasitic inductances.   you output ground connection does not need to be connected to a low inductance path to input ground.  however, the input cap ground needs a low inductance path to the source of the low side MOSFET and the Input cap +ve needs to be connected with a low inductance path to the drain of the HS mosfet..  the loop formed by these components need to be tight.  it's not so much the width of the copper but the loop you are forming that is proportional to the parasitic inductance, as such this layout is not good.  Hence the issues you are having.  Ideally you will want a solid ground plane directly beneath the power stage on the top forming a tight loop, but it's impossible to achieve that here.  so, you will need to layout it out a little differently.  suggest you start with the concept shown below.  different device same concept.  also having two top FETs and two bottom FET further complicates things, perhaps you could get away with a single top and bottom FET?

Hope this helps.

David.