TPS4H160-Q1: Inductive-Load Switching-Off Clamp and Protection for Loss of Power Supply

Hi Patrick,

     It seems you didn't answer my questions directly. I already read the datasheet and had some confusion. I hope you could share your understanding.

    Q1: We could see Vout become negative and stay for a while in Figure 26. Since Vvs stays the same and Iout decreases linearly, so Rdson of FET increases which means FET is turned off slowly. Am I right? Another question is should I expect the waveform I measure to be same with Figure 26? Or this control is only triggered by Vout dropping below Vvs-Vds(clamp）？

    Q2:Am I right?

    Q3:There is a question about "a negative pulse occurs in the GND pin". I guess it's trying to say OUT instead of GND. Because if you take net GND as a reference 0-volt point and the pin has a good connection with the net, I couldn't imagine a negative pulse in the pin. And if OUT is negative and there is a equivalent resistor between IOs and OUT so the current flow is like what I draw. But in this way, I couldn't find how the resistor and diode help to deal the problem.

Hi Tim,

   Q3: Could you explain how the diode&resistor network works? If the current flow like this, what help to protect the system is the resistor between MCU and the device because it can limit the current, in my opinion. Also, what is the max rating voltage of PIN OUT? Because when the circuit below losing supply, inductive load will absolutely cause a large negative voltage on PIN OUT.

Zehui,

We do have a application note that describes loss of battery and inductive discharge here:

https://www.ti.com/lit/pdf/slvaes9

To answer your specific question- the path you listed is correct, however there is also a high impedance path through ground to out (as described in the application note above). The IO protection resistors and the ground network will limit the current and protect the device for applications where there is a very small inductance on the output (typically cabling only <10uH).

Is there any specific concern in your application? Do you happen to have the inductance rating of what is on your load?

Best Regards,
Tim

Tim,

   I read the application note. An approximately 200-kΩ internal parasitic path is much larger than the external resistor. Why the external resistor is needed for limitting the current?

   I am considering removing the ground network because there is some voltage level issue between MCU and the device. So I want to know how the network works for protection.

Zehui,

Is there something like a PFET or ideal diode on the supply side? One of the main purposes of the ground network is so that the device can also survive a reverse battery condition. If this is a concern, to remove the ground network you would need a supply side reverse current blocker. Additionally- for the ISO pulses a ground resistor would be needed here where there is going to be temporary negative/positive spikes in voltage that would allow the effective power to increase (for short pulses). 

The 200k might be a bit misleading here- there is active circuitry here that would require the current going into the ground pin to be blocked (on top of the parasitic resistance). If the voltage drop over the resistor is a concern- the best case would bet to have an ideal diode (or PFET) such as an LM74700-Q1 on the supply line would be the best bet (as well as have other system level benefits).

Best Regards,
Tim

Tim,

    Yes, a TI ideal diode is used on the supply. So I don't worry battery reverse condition. For ISO pulses, could you give more details? I think negative pulse is like a reverse battery which ideal diode could help to protect. What about posiive pulses?

     "The 200k might be a bit misleading here- there is active circuitry here that would require the current going into the ground pin to be blocked (on top of the parasitic resistance)."

      According to datasheet, another purpose of the ground network is supply loss protection, so I need to know how it works, which I still don't understand. If the requirement is blocking the current into the ground pin, a single diode is better while adding a parallel offers a path for current.

     Here is a TI application note Reverse battery protection for high side switches.I don't know if it could help to understand. I don't see a path if the internal MOSFET is turned off. And port like SEH/L and FAULT has a diode blocking the current too.

Tim,

"The IO resistors are there for when current is being drawn through the MCU's supply line, through the MCU IOs, into the HSS to the negative supply. Usually on the MCU supply side there is some sort of diode after a DCDC converter with some bulk capacitance on the output. Even if the supply line  before the DCDC is lost, current will be drawn from this capacitance and could potentially damage the MCU IOs unless there is something to limit the current coming out of the MCU's IOs (which is the point of the resistor)."

 Do you mean there is a path like this?

" Do you have an idea of what the inductance is on your outputs? "

No real inductance load like a relay is on the output. I am sure only parasitic inductance of cable and load exists but I don't know the accurate value.

"The VBB -> ground diode would be the easier solution here as you would only need one from supply pin to ground (versus a separate freewheeling diode across each output load)."

Like this? Offer another current path to reduce the current through internal VBB diode. How could I ensure most current flow throuth external diode? Using a diode with smaller forward voltage?

Zehui,

I am checking with our design and systems team about some of the more detailed workings of the device and will get back to you once I have the complete answer, however would it be possible to take this offline via the email listed in your TI account? This will allow me to loop in more of the relevant engineers to the discussion.

Best Regards,
Tim

Tim,

You can contact me by email.Can you see my email address?

Replied via email.