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TPS4H160-Q1: TPS4H160BQPWPRQ1 How to reach clamp current output and calculate allow clamp current duration time?

Part Number: TPS4H160-Q1

Tool/software:

Hi TI

TPS4H160BQPWPRQ1 driver capacitive load. HSD will clamp current output when inrush current over setting limit value.

I have 2 question

1. How to reach this technology?  I'm guessing you're doing the output current clamping by control the variable resistance region of the MOS

2. how to calculate the HSD die rise temperture?  I need know at 85 deg the HSD allow clamp time? How to calculate?

  • Ling,

    1. This is correct. We are essentially controlling the gate driver in order to keep the FET regulating a constant current (by varying the resistance). The application note that you are referencing goes into the level of detail that we are able to provide.
    2. If you provide us specific loading conditions, we are able to simulate this and let you know about the temperature rise. Using EVMs, we do have the following data:

    With a smaller current limit, you are able to charge more capacitance, however it takes longer to charge.

    Best Regards,
    Tim

  • Thanks what mean of Max Cap (1ms) uF?Is allow capacitance load and inrush current time?

    I want to know how to calculate HSD allow clamp current time,if any tools can support this?

    My load is a capacitance load,inrush current is 10A. Is other loading condition you need?

  • Ling,

    This would be the maximum amount of capacitance that we can charge in 1ms with the spec'ed current limit.

    The best option here would be to test out on the EVM or use the table above as a reference. Do you know what capacitance is on the load specifically? 10A is quite high so there will be considerable power dissipation.

    Best Regards,
    Tim

  • Hi 10A is inrush current,normal current is 0.5A,load capacitance assume 100uF,how to calculate this?