Other Parts Discussed in Thread: TPS543C20A
Tool/software:
Hello,
I am designing a converter using the TPS546E25 with the following specifications:
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Input: 12 V (range: 11.4 V to 12.6 V)
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Output: 4.0 V or 4.5 V
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Load current: 50 A
If you have a TPS546E25 calculation document, please share it.3404.TPS546E25.pdf -
No PMBus used — I intend to apply component values from the TPS543C20A design (since a TPS546E25-specific calculator/document is unavailable).
I would appreciate your help reviewing the design for any potential issues.
In addition, I have two specific questions:
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CNTL (ENABLE) pin:
The datasheet states that the logic HIGH threshold is typically 1.2 V. If I apply 1.8 V to CNTL, will the device recognize it as HIGH and operate normally? -
PMB_ADDR pin:
Since I am not using PMBus, can I leave the PMB_ADDR pin floating, or should I tie it to a defined logic level?
Thank you in advance for your support.