UCC28740: Suspect UVLO problem and get destructive testing

Dear Frans,

Thanks for choosing TI in your design.

I think the waveform you provide is not on the VDD pin. Instead, it is on the auxiliary winding wright?
You can check the UVLO on your VDD capacitor C10 directly.

Or the second picture is on the C10 capacitor.
If is on this capacitor, the reason your circuit can'y work is trigger the UVLO.
You can try increase C10, increase auxiliary winding turns.
You can check the document at 2.1(VSS UVLO):
www.ti.com/.../slua783.pdf

What is your load current during you start up the circuit? If you start the circuit with no load it might trigger OVP function.

The probe on the VDD and DRV pins are ok.

If you have any problems please feel free to let me know.

Best Regards
Kevin

Dear Kevin,

First screen was Vaux yes. I include another one in my following informations.

Second screen was on Vdd capacitor yes.

I’ve already tried to increase C10 capacity (+10uF) but it only increases the time where switcher is inactive, my thought:

Now I think the UVLO is not the problem.

From my previous observation on scope, I could see the switcher (UCC) active during 3ms, then no more activity during 300-500ms that should deactivate the UCC which restart again from HV power.

 

I made test on 100, 300 mA and empty loads.

Here is output with empty load

Here is with 100 or 300mA load (bench electronic charge):

500ms period, 60ms between beginning of rising and return to 0V

We can see here the 3ms activity on the output

Here is activity detail during 3ms(measured on Vds of the Sync Rectifier UCC24636 on 100mA charge) happening every 500ms

 

With a frequency looking correct.

I’ve tested the slua783 2.6.2 Transformer saturation on Vcs: seems no problem

 

 

And last observation I was able to get before 2nd board burn:

3ms activity seen on Vaux

+30/-30V +18V without ringing.

 

Kevin, I’m satisfied by the way you’re exchanging with me and hope we can investigate further.

I’m a beginner on live line power supply (more used of DSP, MCU…) so I’m a little bit nervous testing this stuff.

I would really like to get possible correction before testing and getting it burn again (note previous card was tested multiple hours with very short test run before flashing).

Thank you,

Best regards,

 

Thanks for the constructive answer, but as more describe in my post of March 29 I need more help for my case.

Best regards,

Hello Frans,

Pardon my intercession here. I think I may have a possible explanation for the problem that you are seeing.
I see n your schematic drawing that the divider resistors for the synchronous rectifier controller UCC24636 at the VSC input has 97.4K ohm to GND and 47.5K to Vout. I don't have all of your design parameters available, but assuming a typical situation of 85Vac input min (Vin(min) down to ~70V or so) and 5V out, I think the VSC connection is going to the wrong node.
I suggest that maybe it should be 49,.9K to GND and 2x47.5K to Vout.

The consequence of the connection shown in the schematic is that VSC will be too low and the SR on-time will be extended too far.
The SR would still be on when the next primary turn-on interval happens, which would produce a shoot-through pulse.

This would trigger over current and shut down the primary controller, with continual retries.
It doesn't happen earlier because the SR controller won't start up until Vout reaches 4V.
At no load, Vout will hold 4V for a relatively long time and a shallow decay slope (as shown in one of your waveforms).
But adding a load will pull Vout down very quickly.

Please investigate the VSC connection and see if that is the cause of these shutdowns.

Regards,
Ulrich

Hello Ulrich,

This is a pleasure to be interceded like this.

After checking the UCC24636 design calculator spreadsheet data I generated for my project. Yes, the Vcs branch of the SR was badly wired.

I will correct and test this on PCB shortly.
But do you think such error could cause switch chip fault and destruction?
I hope so.

Thank you greatly for your observation. Can't believe you was able to spot this mistake on another people design.

Best regards,

Frans.

Sorry after modification (on SR Vcs branch) and short test I still have unstable output.

Switcher is still pulsing during around 3ms and restart activity after ~600ms.

And we can see switcher going in protection after the 3ms and the Vdd depleting till 7V and switcher restart.

Output under 100mA load:

And output + switcher Vdd(blue):

I feart to push test more longer as it seems last correction doesn't solve the main problem and I fear to destroy this 3rd board.

Have you any advice on what to test/measure in priority? (I will have on more look on the SLUA783 Troubleshooting TI PSR Controllers, to find also by myself)

Thank you for your attention.

Best regards,

Hello Frans,

I’m sorry that you are still encountering trouble, but at least we’ve gotten past the VSC connection issue.

I looked up the transformer part number at Wurth Electronics and it shows an 18:7 turns ratio from AUX to SEC. The UCC28740 has an overvoltage protection (OVP) threshold of 4.6V at the VS input. Working backwards from this using the R10 and R15 values in your previous schematic, I get: (4.6V/23.7K)*47K+4.6V=13.722V at Vaux reflected from the secondary. Then 13.722/18*7=5.336V at Vsec.

Whether the SR-Fet V-drop is accounted for or not, this is a rather low voltage for OVP. I think there may be a little overshoot during start-up that is exceeding 5.3V and triggering OVP shutdown and retry.
I suggest to try a ~15% OVP (5.75V assuming ~0V for the SR drop) and reduce R15 value to ~21.2K, maybe by adding a 200K resistor across the 23.7K as a quick test.

As an aside, if you look at the ‘scope screenshot of Vout plus VDD, you can see significant curvature in the VDD signal as it ramps up and down between the UVLO off and on thresholds. I believe this is due to the DC-bias effect that plagues multi-layer ceramic capacitors with high-K dielectrics such as X7R, etc. specifically in small-packaged parts. There can be a surprising drop in capacitance value with applied DC voltage. The smaller the case size, the more pronounced this effect is. With a web search, you may find information about this on the MuRata website or other vendor sites.

This may or may not be a problem, depending on whether the C10 cap value is specified with this effect taken into account or not. If not accounted for, VDD could deplete to the UVLO shutdown threshold sooner than expected, for example, while waiting for Vout to settle from an overshoot after a step-change from full-load to zero-load, while the switching frequency is minimal.

Anyway, good luck with your debug. I hope the OVP setting accounts for this issue you have at the moment.

Regards,
Ulrich