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UCC28950: Ucc28950 current transformer pacement. transformer saturation.

Slavko skala
Prodigy 150 points
Part Number: UCC28950
Other Parts Discussed in Thread: TINA-TI

Hello dear hosts!

I have two separate questions about ucc28950 application:

1)could current sensing transformer be moved from the supply rail to the transformer's primary? will controller operate correctly with ct in the power transformer primary?

2)should dc blocking capacitor be placed in series with transformer's primary to prevent core saturation in the situation when pwm duty cycle changes. so when previous duty cycle is different from the current,transformer does not get a dc bias that can saturate the core?

Thank you!

  • 0
    Prodigy 150 points
    When using current transformer on primary of main transformer it could be connected to the controller scheme via shottky diode bridge rectifier,to make use of both semi periods of current?
  • 0 in reply to Slavko skala
    TI__Mastermind 25570 points
    Hi Slavko

    I think my earlier post at e2e.ti.com/.../698268 answers your first question - My own opinion is that it is best placed in the supply rail.

    Yes - if you are putting the transformer on the primary of the main transformer then you MUST measure the current in both half periods - otherwise the controller won't 'know' when to terminate the PWM cycle of the bridge during the 'no measurement' half cycle.
    So rectification could be done using schottky diodes or 'normal' signal diodes. Just make sure that the increased leakage current of the schottky diodes when they are reverse biased doesn't give you a false reading.

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    Prodigy 170 points
    I recently was told that if you use primary side sensing you cannot put a capacitor in series of transformer. Could you comment on this Colin.
  • 0 in reply to Bob LaFrance
    TI__Mastermind 25570 points
    Hi Bob

    That's an interesting question - I'll have to do some more work on it but for now this is what I know

    There is an inherent instability in the half bridge topology under peak current mode control where any imbalance in the splitter capacitor voltage will increase until one capacitor has zero volts across it and the other has the full input voltage across it. I'm not sure if this instability is present on all topologies with a DC blocking capacitor and to be honest it is not something I had heard about previously. If you have a reference source - I'd be delighted if you could share it.

    This is a different instability to the sub-harmonic oscillation which happens at wide duty cycles and for which slope compensation is the usual solution.

    This divergance is not present under Voltage mode or Average current mode.

    I ran some simulations in TINA-TI using the UCC28950 model - I didn't see any divergance even if I put in a fairly significant initial asymmetry. BUT - I'm not convinced yet and I need to do some more work on this - please bear with me - it may take a few days.

    Regards
    Colin
  • 0 in reply to Colin Gillmor
    Prodigy 170 points

    Hi Colin.

    I will pass this link to the person who told me of problem and invite him over.

    regards,

    Bob

  • 0 in reply to Bob LaFrance
    Prodigy 170 points

    I think the peak current mode control will cause the cap to eventually rail out.

  • 0 in reply to Bob LaFrance
    TI__Mastermind 25570 points

    Hi Bob

    A half bridge converter under peak current mode control will indeed rail out where one splitter cap charges down to 0V and the other cap charges up to Vin. There are a number of ways of preventing this of course but...

    Over the past few days I've had several Phase Shifted Full Bridge simulations running in peak current mode control with a series capacitor and the system always stabilises despite my attempts to put in asymmetries like different resistances in the primary paths and large voltage steps on the capacitor. I think the fundamental difference between the half bridge and the PSFB here is that the current in the primary of a PSFB is present during the power transfer AND the freewheeling parts of the cycle whereas in the half bridge it is present only during the power transfer part of the cycle. I'm trying to understand this more fully before quantifying it.

    I'll continue to work on this here but if you want to try it yourself you can simply download the slum277 TINA-TI schematic from the UCC28950 product datasheet.http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slum277&fileType=tsc

    I modified it to put a 1uF cap in series with the primary. I also added a 0/50V step generator in series to give the system a large imbalance. (Setting the transient to come on at about 3.5ms works well)

    Regards

    Colin

  • 0 in reply to Colin Gillmor
    Prodigy 150 points

    Hi Colin! i have finally built a converter using 28950,a scheme i used as in datasheet: current transformer in supply rail,dc blocking capacitor in primary winding,etc... but controller shows strange behaviour in one leg its C and D outputs (A and B are fine). take a look at oscilogramm of ucc28950 C output and gate transformer output (yellow trace its transformer). iam using tc4420 gate drivers on each output

    should ucc28950 controller give such narrow and wide pulses on one leg and regular pulses on other leg? what can be the issue? i changed chips and situation looks the same!

  • 0 in reply to Slavko skala
    TI__Mastermind 25570 points

    Hello Slavko

    In the steady state the OUTA, OUTB, OUTC and OUTD signals are always 50% duty cycle with a phase shift between the OUTA/OUTB pair and the OUTC/OUTD pair. When the control system tries to change the phase shift then OUTC, OUTD pair will be slightly greater or less than 50% - but this is a transient condition. What you are seeing is much more severe.

    What is the operating condition ? for example when this happens is the controller operating at Dmax and in current limit?

    Are there any operating points where the system is stable

    Are you running any of the OUTx signals directly under the IC body? or close to the CS line ? either of these can inject noise into the controller and upset it.

    The only time I have seen OUTC/OUTD looking anything like what you are showing above was if the controller was being synchronised to a SYNC signal whose frequency was much lower than the recommended limit (1.8 times the free running frequency)

    Please send me your PCB layout (Gerber files or native s/w files are good) and I'll have a look over them. If you don't want to publish them here then you can send them to me directly at colingillmor@ti.com

    The file below is a Power Point slide with an embedded animation showing how the PSFB generates the duty cycle across the transformer - you probably know this already but it's a useful reminder nonetheless. Do let me know if the link does not work.

    /cfs-file/__key/communityserver-discussions-components-files/196/7870.Animation.pptx

    Regards
    Colin

  • 0 in reply to Colin Gillmor
    Prodigy 150 points
     it seems that i have found a reason of output CD duty cycle issue!

    i was experimenting and i found that capacitor on CS signal was cracked.when i was soldering around him,he broke apart. when i replaced him with a normal one extreme duty cycles dissapeared! but still it gets to 38%. is it normal for this controller to have 38% or 62% duty cycle

  • 0 in reply to Slavko skala
    TI__Mastermind 25570 points
    Hi - As a follow up to Bob's earlier question about the stability of the PSFB in Peak Current Mode control when there is a DC blocking capacitor in series with the circuit. I've been simulating various scenarios where the DC blocking capacitor is present and they are all stable. This includes CCM with SRs, CCM with Diodes, Centre Tapped Secondary and single winding secondary with full bridge rectification. I also looked at DCM. All these conditions are stable.

    The Half Bridge is not stable under PCM of course and the fundamental difference between the Half Bridge and the PSFB is that in the PSFB current flows in the blocking capacitor during the entire switching cycle, Ton and Toff. Any error in the charge on the capacitor at the end of Ton is corrected - at least partially during the following Toff and Ton intervals.

    I am closing this thread now because the initial problem that Slavko had is resolved and the blocking capacitor issue is somewhat off topic.
    But - I will write up a clearer explanation of why the PSFB with a DC blocking capacitor is stable inPCM over the next few weeks and publish it as a blog. This will be a background task for me so it may take some time. In the meantime if anyone has any specific questions about this then please get in contact with me - either raise a new e2e post or email me directly at colingillmor@ti.com

    Colin
  • 0 in reply to Slavko skala
    Prodigy 150 points
    I have sold that issue! Rsum was too big (value from excel sheet). i have placed 10 times smaller value and controller gave me good signal on all outputs.
  • 0 in reply to Slavko skala
    TI__Mastermind 25570 points
    Excellent - Thanks for the update.

    Regards
    Colin