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PTH04T241WAS Powerup Issue

Jianbo Pan
Prodigy 10 points
Other Parts Discussed in Thread: TPS40100

Hi,

I'm using PTH04T241WAS as my MPC8548 PowerPC CPU core power supply. The input is 3.3V, and the output is 1.1V.

In the operation, when the output 1.1V ramps to 0.4V, we can find inrush current happens on the 3.3V rail. And this inrush current is far higher than all I/O current, most importantly, it causes the 3.3V drop. This is harmful for other devices connected with 3.3V power plane. The inrush last time is about 800uS.

We changed the soft start capacitor's value to 10nF on the module(which connects with TPS40100's SS pin), the inrush last time decreased, and it also happened when 1.1V output ramped to 0.4V. Futhermore, we found that if the 3.3V doesn't finish discharging, and then we powerup again, the inrush will dissappear!

In our application, the tracking function is disabled by connecting the TRACK pin directly with Vin(3.3V), and sense function is also disabled.

In our system, because there is only one 3.3V rail input, that means we power up the I/O supply prior to core supply, and this is allowed by MPC8548 spec.

My questions are:

1. Is it possible that this issue is caused by pre-bias start-up?

2. What other factors can cause this issue?

Need experts here help to take a look at this issue, thanks a lot in advance.

 

 

  • 0
    TI__Mastermind 38230 points

    the  issue appears to both maximumstart-up  current required by the MPC8548 and the power sequencing  event . You should contct Free sc ale on this question.

    The power and sequecing of voltages is attached .

    A secion from their data sheet is below.2.2

    Power Sequencing. The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power-up:1.VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD2.GVDDAll supplies must be at their stable values within 50 ms.NOTE Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.NOTEIn order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is

    Pages from fMPC8548psp=1power up sequencing .pdf