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UCC28950: Forced CCM Synchronous FET Failure

Christopher Arntzen
Intellectual 580 points
Part Number: UCC28950
Other Parts Discussed in Thread: UCC28951, UCC29002

Hello,

On page 28 of the datasheet for UCC28950, SLUSA16D, it states "DCM must be used in order to prevent reverse current in the output inductor which could cause the synchronous FETS to fail."  In what way could the synchronous FETs fail?  And if they would fail, why does the chip have a forced CCM option?

  • 0
    TI__Mastermind 25570 points

    Hello Christopher

    There are a couple of conditions to consider here:

    First - If diode rectification is used then the DCM function is redundant and the DCM pin can be tied to VREF. This disables the OUTE and OUTF signals for a small reduction in system noise. Or the DCM pin can be tied to GND and the OUTE and OUTF signals will be present and the pins may be left open circuit. The inductor current will always be positive because the diodes can't conduct in the reverse (negative) direction.

    Second - the SRs can be allowed to run at all load currents from 10)% to 0% by tying the DCM pin to GND. This technique is used in the PMP5726 reference design where it helps to improve the no load to full load transient performance.

    Third - If SRs are used then it is usual to use the DCM pin to disable the SRs at some light load level and the SRs revert to operating as simple diodes. As the load current reduces, the inductor current becomes discontinuous and the duty cycle starts to reduce as the load reduces. Eventually the duty cycle gets small enough that the minimum Ton time as set by the TMIN pin is reached. As the load reduces further the controller operates in burst mode. The overall effect of this process is to improve light load efficiency by eliminating SR gate drive power and having the system run in a burst mode rather than at increasingly narrow Ton times.

    The SR will conduct in both directions while its channel is enhanced. It will pass positive current from its source to its drain and negative current from its drain to its source without any problems. However, if the SR is turned off while the current is negative - from its drain to its source - then any stray inductance in the current path will generate voltage spikes - normally showing up as voltage spikes on the Drain to Source of the SR. The voltage will probably be high enough to cause the SR to avalanche and depending on the amount of energy available and its robustness it can fail short.

    BTW: I'd reccommend that you consider using the UCC28951 - this is a 100% compatible device which offers better performance at wide duty cycles  there are some more details at http://www.ti.com/lit/pdf/SLUA853 

    Regards
    Colin

    Regards

  • 0 in reply to Colin Gillmor
    Intellectual 580 points

    Would there be any other failure mode for a synchronous FET if two or more phase-shifted bridge outputs were paralleled using the UCC28950?

  • 0 in reply to Christopher Arntzen
    TI__Mastermind 25570 points

    Hello Christopher

    Normally when two or more PSFB stages are paralleled we use one as a Master and the other(s) as slaves. This forces each power stage to deliver equal currents to the load. If this is not done then there is a possibility for the power stage with the highest output voltage to backfeed current into the output of one of the other stages. This will be inefficient and will give a lossy condition in the power stage being backfed because the stage will lose ZVS (the currents are in the wrong direction).

    Other than that there are no problems and paralleling stages in this way is actually quite commonly done, here's a sketch of the general arrangement. /cfs-file/__key/communityserver-discussions-components-files/196/4426.Paralleling-two-UCC28950.pdf

    Regards

    Colin

  • 0 in reply to Colin Gillmor
    Intellectual 580 points

    What if the two or more outputs are not setup as Master / Slave?  I am paralleling up to three phase-shifted bridges that are independent of each other and not synchronized.  What are the potential hazards to the synchronous FETs in that case if running in CCM versus DCM?

  • 0 in reply to Christopher Arntzen
    TI__Mastermind 25570 points

    Hi Christopher

    The danger is that the bridge with the highest output voltage will back-drive current into the one or other or both of the other two power stages. I don't think this is immediately catastrophic for the backdriven PSU but it's undesirable. I don't think that whether the controllers were synchronised or not would make any difference. Normally in this case ORing diodes (or oring FETS) are used - like those at http://www.ti.com/power-management/power-switches/ideal-diodes-oring-controllers/products.html

    It is also possible to force current sharing using an external load share controller like the UCC29002/1.

    Regards
    Colin

  • 0 in reply to Colin Gillmor
    Intellectual 580 points

    Hi Colin,

    I have a more specific question regarding the failure:

    I am running three phase shifted bridges in parallel that are not sunk and each have an error amplifier external to the UCC28950.  I am current sharing them by connecting the outputs of the error amplifiers together through diodes and to the EA+ pin of the UCC28950, so one error amplifier regulates all three supplies and they do current share well.  The COMP pin is connected to EA-, so the internal error amp is a voltage follower.  The UCC28950s are all set up for forced CCM.  I am having synchronous FET failures during turn off.  The three supplies turn off at different times and the supply that turns off first sources a large current (150A) into the other supplies.  The current oscillates back and forth between the supplies at about 20kHz an finally dies out.  The synchronous FETs of the other two supplies keep switching and when this large current flows drain to source when they turn off, there is a large voltage spike that exceeds the Vds rating of the FETs, which I believe is causing avalanche breakdown of the FETs.

    I am going to use DCM at light loads to prevent reverse current in the synchronous FETs.  Will this completely solve my problem and prevent the synchronous FET failures?  Is there another solution to prevent the failures?  Is there any more insight you can give me? I'd like to discuss on a phone call to better explain the scenario and ensure that these failures do not occur under any circumstance.

  • 0 in reply to Christopher Arntzen
    TI__Mastermind 25570 points

    Hello Christopher

    We can certainly have a telephone conversation - with WebEx too. Your explanation is clear but I'd like to see your schematic and any test results you have first so that I can be sure I understand what you are doing. If you don't want to post the information here then please send it to me directly at colingillmor@ti.com

    Regards

    Colin

       

  • 0 in reply to Colin Gillmor
    Intellectual 580 points

    Hi Colin,

    Did you get my email from yesterday?  Could you please set up a WebEx for 9am Pacific time today?

    Thanks,

    Chris

  • 0 in reply to Christopher Arntzen
    TI__Mastermind 25570 points

    Hi Christopher

    We've taken this discussion off this forum and onto email / phone. I'm going to close this thread. You can open a new or a linked thread if you wish.

    Regards

    Colin