Hi Mathew,

As per application schematics, enable of power stage (CSD95496QVM) controlled by ASKIP# pin of TPS53622A.

In application schematics, enable of power stage is suggested to be connected to 5V VDD.

Is ASKIP and BSKIP pin able to control the power stages without AVR_EN & BVR_RN? Is AKSIP and BSKIP pin active functionality once 3.3V rail up?

While VREF of TPS53622A is ready, ASKIP/BSKIP will be the voltage of VREF (1.7V), then it will go high along with AVR_EN or BVR_EN is high.

Thanks,

Chasel

Hi Mathew,

Please get datasheet for following questions.

1. Is SMBUS of TPS53622A( VR13 regulators) can connect with CPLD to monitor Telemetry reading and Other programmable configuration setting?

Yes.

2. Do we have any sample code for SW configuration and please share if available?

Please download fusion GUI here

http://www.ti.com/tool/FUSION_DIGITAL_POWER_DESIGNER

Select Offline Mode - Create new Offline system from start - Select Device - TPS40xxx/TPS53xxx/… - Select TPS53622

There is minor difference between TPS53622A and TPS53622. Tracking OVP is selectable regardless VR mode, please find datasheet for detail. You can use TPS53622 sample code without issue.

3. Do we need to initialize any SW before power ON the board or default configured in factory?

It depends on your design, please check the default settings in the table of datasheet, if the initial NVM settings don't match the design, you will need to pre-program TPS53622A before EN is high.

4. Do we need any Header connector for programming the TPS53622A (VR13 regulator) ?

You will need PMB_CLK/DAT/GND.

Thanks,

Chasel

Hi Mathew,

What is Maximum length of sense trace (AVSP /AVSN) b/w VR13 regulator and SOC.?

There is no limitation of VSENSE traces. Certainly, as short as possible, and couple of proven design are with 12inches length without any issue as long as the traces route in quiet area. (no switching noise and refer to GND).

SOC supports only VCCCPU and VCCRAM sense lines. Using two VR13 regulator to generate VCCCPU, VNN, VCCRAM and VDDQ rails.  VCCCPU and VCCRAM sense traces are connected with SOC.  What about VNN and VDDQ sense traces? Need any termination if unused? Please suggest 

You can tie the sense line to the load if there is no connection needed of CPU.

AVR_RDY/ BVR_RDY output pin indicates when VR13 controller is ready to accept SVID commands.  How processor know this information to proceed SVID transaction? What is function of this pin?  Shall this pin for Power Good output and connect with CPLD?

This is system related question, you can check with your customer to see how they achieve this. I cannot provide anything here as it is Intel proprietary information.

SMB_CLK/ SMB_DIO/SMB_ALERT# pin names are SMBUS or I2C.  In Specification mentioned as PMBus. Could you please confirm the TPS53622A supports PMBus or SMBus? Shall we tie this interface with SMBus or I2C?

SMBUS is better, but I2C is ok if engineer can translate the protocol to SMBUS/PMBUS by I2C.

Thanks.

Chasel

Hi Sheik,

http://www.ti.com/lit/pdf/slua888

You can use TPS53679 programming tool for TPS53622A which is with same footprint.

Thanks

Chasel

Hi Sheik,

1. Are enable pins (AVR_EN and BVR_EN) of SVID controller has an internal pull-down? Do we need an external pull-down? We are driving this pin from CPLD and during initialization of CPLD, what is the state of this enable pins?

You will need to pull AVR_EN / BVR_EN low if no use. That means keep CPLD status as low before you want to enable the power.

1. Placement for VCCP and VNN sense resistors?

Follow intel PDG.

1. Why there is delay network placed for AVREN and why not for BVREN in the application schematics in the datasheet?

It is just an example, you can decide to use it or ignore it.

1. Why there is 0 ohms Resistor placed b/w VREF and VREF_P in application schematics in the datasheet?

Only for debugging purpose

1. Input Current sense signals for SVID controller is de-poped in TI reference schematics. How path will close to sense input current?

You can use Calculated IIN instead if input current shunt is not used.

Thanks

Chasel

Hi Sheik,

We already got the same file from sales team, you will get the comments later.

Thanks.

Chasel

Hi Sheik,

There is no special requirement of this connector, just make sure it is 2.54mm pitch, but you can refer to TSW-105-07-G-D.

Thanks

Chasel.

Hi Sheik,

If it is 2.54mm pitch, then it is ok.

Thanks

Chasel