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LM5116: SW node ringing exceeding 100V

Part Number: LM5116
Other Parts Discussed in Thread: LM25149-Q1, LM5146-Q1, LM5143-Q1, LM5164

Hi there, 

I have an LM5116 design that operates on 48-85Vin, 12Vout, 1.5A.

I'm trying to reduce the amplitude of the ringing on the switch node, as the peak exceeds 100V when operating at Vin = 85V.

I have based my layout on snva803 by:

- Placing input capacitors as close to the MOSFETs as possible.

- Using 3mmx3mm package MOSFETs for low parasitics with a low Qrr value.

- Keeping the main power loop area as small as possible.

- Generally making the layout as tight as possible.

With the circuit schematic and layout attached, the switch node ringing exceeds 100V - measured using a ground clip, not the long ground lead.

I have made the following changes to the schematic to try and reduce the peak of the ringing:

1) Increased the HS gate resistance from 0Ohm to 20Ohm - reduced peak from 109.3V to 101.3V.

2) Added an RC snubber circuit to the switch node, 2.2Ohm and 100pF - reduced peak to 98V.

Here is what the SW node looks like (the snubber did a good job at dampening the ringing):



I would like to reduce the ringing further. Considering the input voltage is 85V, ideally I would like to get the ringing down to <95V, as I've found the LM5116 is the first components to fail if the input voltage rises slightly above 85V.

I don't think there are significant flaws in my PCB layout, would you agree? 

Is there anything else I can try to reduce the peak of the ringing, if it's a MOSFET issue, what MOSFET parameters should I pay the most attention to?

Any help would be greatly appreciated!

Ben

  • Hi Ben,

    Another option here is to disconnect VCCX from VOUT and rely on the internal VCC. This lowers the gate drive amplitude and hence reduces the turn-on speed. The penalty in terms of no-load input current is not that big as these FETs are low gate charge. Note that it will be difficult to get the overshoot below 10V above Vin as there is an inherent amount of parasitic loop inductance in the design (FETs, input caps, PCB traces). Option #3 in app note snva803 is the best layout technique for minimizing that parasitic inductance, and this technique is now used in the LM5143-Q1, LM5146-Q1 and LM25149-Q1 EVMs with good results.

    Regards,

    Tim

  • Hi Tim, 

    Thanks for the prompt reply.

    I'll try disconnecting VCCX from Vout and see if the ringing amplitude decreases and if the thermals are still okay. I agree that layout #3 in SNVA803 makes the most sense in terms of current loop area.

    In my current layout, I have quite a large copper area on the top layer as well as on the bottom layer connected to the switch node to help with heatsinking. Would this extra copper effectively increase the switch node inductance, despite the inductor being located directly next to the MOSFET, contributing to ringing also? I noticed that on layout #3, the copper pour between the switch node and inductor has been minimized in size as much as possible.

    As you mentioned in your reply, I might struggle to get the ringing overshoot below 10V with this LM5116 design.

    As the load current is quite low (I've worked out that I actually only need roughly 800mA), would you agree that the LM5164 is a safer, low risk option? My thinking is that the switches are internal so overall the parasitics are lower and the ringing overshoot won't exceed safe levels if the layout is done correctly. 

    Many thanks,

    Ben

  • Hi Ben,

    SW copper does not affect the critical loop inductance arising from the FETs and the input caps.

    Yes, the LM5164 is a better option here if the output current is less than 1A. The integrated FETs will provide much less overshoot - you can measure it on the EVM as a starting point.

    Regards,

    Tim