Part Number: AM625
Other Parts Discussed in Thread: AM62P, AM62D-Q1, TPS65224-Q1, AM6442, TDA4APE-Q1
Tool/software:
HI TI experts,
I have queries related to supported reset inputs and reset status outputs
Supported Reset inputs
Recommended connections for Reset inputs
Supported Reset Status outputs
Recommended connections for Reset Status outputs
HI Board designers,
Please refer below.
Supported Reset input and output signals
AM64x
AM243x (ALV/ALX)
AM625
AM62A
AM62P
Connection recommendations
AM64x/AM243x/AM62x/AM62Px/AM62Ax/AM62D-Q1
MCU_PORz
Leaving MCU_PORz unconnected is not allowed or recommended. Connect to a valid reset input with minimum slew. use a 22-pF glitch filter.
Warm reset input
Reset Status output
Add a pulldown to hold the attached device in reset during supply ramp.
When not connected to any attached device add a TP for testing.
Regards,
Sreenivasa
Hi Board designers
Please refer below inputs for MCU_PORz, RESET_REQz and MCU_RESETz reset inputs slew rate requirements:
The Electrical Characteristics tables defines capabilities of a specific IO cell. It does not define a how the IO is configured to operate. You need to reference the Pin Attributes table to understand how the IO associated with each pin is configured to operate. For example, the AM64x RESETSTATz signal function is implemented such that it is "Off / Low / Off" while MCU_PORz is asserted and "Off / SS / Off" after MCU_PORz has been de-asserted. This indicates the input buffer associated with the RESETSTATz pin is turned off during and after reset. The output buffer associated with the RESETSTATz pin is enabled during and after reset, where the output is actively driven low during reset and controlled by the reset subsystem after reset. The internal pull resistors associated with the RESETSTATz pin are turned off during and after reset.
In summary the RESETSTATz pin is an always enabled output only pin, where Vol, Voh, Iol, and Ioh are the only parameters defined in the LVCMOS Electrical Characteristics table that applies to the LVCMOS IO that is being used to implement the RESETSTATz pin.
TPS65224-Q1 nRSTOUT for MCU_PORz
Please keep in mind the AM62Ax device requires the MCU_PORz input to have a maximum rise/fall time of 1000ns. This may be difficult to achieve with a pull-up on a signal sourced from an open-drain output buffer. You may need to buffer the open-drain signal with a push-pull buffer that has hysteresis on its input to ensure the AM62Ax device never receives a short reset pulse that violates the minimum pulse duration defined in the "MCU_PORz Timing Requirements" table. For example, it may be possible for noise to couple on the slow rising open-drain signal just as it crosses the input buffer threshold which could cause a short glitch on the reset signal. Normal device operation could be compromised if this occurs.
See the "Input Slew Rate" parameter in the "Fail-Safe Reset (FS RESET) Electrical Characteristics" table.
The MCU_PORz input is the only input on the AM62x device that is fail-safe and 3.3v tolerant. Therefore, you can pull the MCU_PORz signal to 1.8V or 3.3V.
See the "Steady-state max voltage at all fail-safe IO pins" parameter for MCU_PORz in the "Absolute Maximum Ratings" table.
important point about the MCU_PORz input slew rate. It is very easy for noise to couple on slow rising signals such that it creates non-monotonic transitions. Your MCU_PORz reset source needs to be monotonic to prevent the chance of creating glitches on internal reset as it transitions through the input buffer switching threshold. A faster slew rate on the MCU_PORz will increase your system noise immunity. The min slew rate defined in the AM62Ax datasheet is acceptable to the AM62A device but may not be acceptable for your system noise immunity requirements.
We define a minimum slew rate in the SOC datasheet for inputs and this creates a maximum rise time requirement. The rise/fall time for the reset signal must be less than 1000ns, not greater than 1000ns. To ensure your design meets this requirement, you may need to use a buffer between the PMIC and SOC or select a pull-up resistor value that is strong enough to charge your PCB parasitic capacitance and the SOC input capacitance in less than 1000ns. A rise significantly faster than 1000ns is preferred to minimize the potential of noise coupling to the reset signal.
We have discussed on the cold reset input MCU_PORz having internal hysteresis enabled and the need to apply signal with Min slew or use a discrete push pull buffer to avoid glitching of the internal reset.
Does the MCU_RESETz and RESET_REQz warm reset inputs implement similar hysteresis and the above recommendations be valid for these warm reset inputs.
The real concern with reset is creating a short assertion pulse. The reset is asynchronously applied to all flops in the device. However, it takes some time for the reset to propagate to all of the flops. Creating a short assertion pulse could allow some flops to be reset and other flops not to be reset if the assertion pulse width is less than the time it takes for the asynchronous reset to propagate to all flops. If this happens, the unexpected start condition could cause state machines to do unpredictable things. So yes, the concern is that a slow transition through the input buffers switching threshold along with noise in the system could generate a glitch on the internal reset signal, which creates a shorter than expected reset assertion pulse.
To answer the first part of your next question, you simply need to look in the datasheet.
For the second part of your question, the datasheet defines the same minimum active pulse width of 1200ns for both MCU_RESETz and RESET_REQz inputs that was defined for MCU_PORz. Therefore, I think these reset inputs have the same requirements as MCU_PORz.
The Hysteresis in enabled for the IO that support hysteresis using PADCONFIG register. the hysteresis is enabled by default.
Regards,
Sreenivasa
Hi Board designers,
Usually add RC filter on RESET signal to anti noise, but the slew rate requirement of RESET signal on AM62x datasheet is quite sharp, on customer board it is about 10V-100V/ms, can it meet AM62x reset requirement, if not please help to explain the basic mechanism.
There can be long-term reliability issues associate with the input buffer if the applied signal spends too much time in the voltage region between VIHSS and VILSS. The maximum transition time allowed is 1000ns. I recommend driving the reset input with a push-pull buffer that produces a signal transition rate that is faster than 10ns to eliminate the risk of noise coupling into the signal as it transitions through the input buffer switching threshold.
A 22 pF glitch filter is recommended at the input of MCU_PORz
another important point about the MCU_PORz input slew rate. It is very easy for noise to couple on slow rising signals such that it creates non-monotonic transitions. Your MCU_PORz reset source needs to be monotonic to prevent the chance of creating glitches on internal reset as it transitions through the input buffer switching threshold. A faster slew rate on the MCU_PORz will increase your system noise immunity. The min slew rate defined in the AM625 datasheet is acceptable to the AM625 device but may not be acceptable for your system noise immunity requirements.
Please keep in mind the AM62x device requires the MCU_PORz input to have a maximum rise/fall time of 1000ns. This may be difficult to achieve with a pull-up on a signal sourced from an open-drain output buffer. You may need to buffer the open-drain signal with a push-pull buffer that has hysteresis on its input to ensure the AM62x device never receives a short reset pulse that violates the minimum pulse duration defined in the "MCU_PORz Timing Requirements" table. For example, it may be possible for noise to couple on the slow rising open-drain signal just as it crosses the input buffer threshold which could cause a short glitch on the reset signal. Normal device operation could be compromised if this occurs.
See the "Input Slew Rate" parameter in the "Fail-Safe Reset (FS RESET) Electrical Characteristics" table.
The MCU_PORz input is the only input on the AM62x device that is fail-safe and 3.3v tolerant. Therefore, you can pull the MCU_PORz signal to 1.8V or 3.3V.
See the "Steady-state max voltage at all fail-safe IO pins" parameter for MCU_PORz in the "Absolute Maximum Ratings" table.
Regards,
Sreenivasa
Hi Board designers,
FAQs for reference
1. Is there any problem that is expected when simplified with POWER-ON and Cold RESET as above circuit?
This is not adequate for MCU_PORz. Please review the reset section 7.10.3.1 and figure 7-3 of the datasheet. MCU_PORz should be low throughout the power up sequencing and remain low for 9.5ms.
Regards,
Sreenivasa
Hi Board designers,
Use of RESETSTATz for resetting attached devices:
Customer is asking for if our AM62x EVM design for resetting eMMC using an AND gate (see schematics) is a solution we would also recommend for series production ... or do we consider that as a functional demo only?
The AND gate produces an eMMC device reset when either RESETSTATZ is asserted low or the GPIO connected to GPIO_eMMC_RSTn is asserted low. The RESETSTATZ signal will be asserted when the AM62x receives a cold reset or a warm reset. This signal is needed to ensure the eMMC device is returned to its initial operating state any time the AM62x device is reset. The GPIO_eMMC_RSTn is provided to allow the eMMC software driver to reset the eMMC device in case it wants to reset the entire eMMC subsystem.
You will need to check the eMMC software driver you plan to use to know if this function is available and to understand how you tell it which GPIO was used for this function.
(+) AM623: AM623: Question on SK-AM62 Design - Processors forum - Processors - TI E2E support forums
U58 is an AND gate, so the output is only high when inputs 1 and 2 are high, otherwise it is low. However, there is also an up pull on the RST side, so the RST side is always high, right?
Please help explain, thank you
The GPIO controlled input originates from a AM62x IO that is turned off until the eMMC driver software initializes it to be a software-controlled reset output. The input allows the eMMC software driver to reset the eMMC device without resetting the entire system. The external pull-up on this signal is required to hold the undriven signal high until software initializes the associated GPIO. The device would not be able to boot from eMMC if the signal had an external pull-down attached since the ROM codes doesn't know which GPIO is used to implement a software reset.
The RESETSTATz input will be driven low when the AM62x device is being reset (power-on reset or warm reset). This input allows the eMMC device to be reset for the first time after the system receives power or if the AM62x device encounters a warm reset event like a watchdog timeout.
(+) [FAQ] AM6442: AM6442 LVCMOS Buffer Type - Processors forum - Processors - TI E2E support forums
In the datasheet of the AM6442 RESETSTATz signal is defined as LVCMOS buffer type.
LVCMOS buffer type is described below as a push pull cell with those caracteristics :
Could you please for more understanding provide a diagram of this LVCMOS cell. I'm confused if this push pull cell drives throught a pull up / down resistor its output between 15k ohm and 30 k ohm.
The Electrical Characteristics tables defines capabilities of a specific IO cell. It does not define a how the IO is configured to operate. You need to reference the Pin Attributes table to understand how the IO associated with each pin is configured to operate. For example, the AM64x RESETSTATz signal function is implemented such that it is "Off / Low / Off" while MCU_PORz is asserted and "Off / SS / Off" after MCU_PORz has been de-asserted. This indicates the input buffer associated with the RESETSTATz pin is turned off during and after reset. The output buffer associated with the RESETSTATz pin is enabled during and after reset, where the output is actively driven low during reset and controlled by the reset subsystem after reset. The internal pull resistors associated with the RESETSTATz pin are turned off during and after reset.
In summary the RESETSTATz pin is an always enabled output only pin, where Vol, Voh, Iol, and Ioh are the only parameters defined in the LVCMOS Electrical Characteristics table that applies to the LVCMOS IO that is being used to implement the RESETSTATz pin.
Regards,
Sreenivasa
Hi Board designers,
FYI
RESETSTATz during reboot (software warm reset)
after each reboot, RESETSTATz will be pulled low for 220 µs, and eMMC_RSTn is affected by the action of RESETSTATz.
Regards,
Sreenivasa
Hi Board designers,
FYI related to reset input causing the bord not to boot.
(+) AM623: Stuck in Reset - Processors forum - Processors - TI E2E support forums
The MCU resetz and warm reset (reset_reqz) seems to be controlled by the MCU.
Can you please confirm the signals are high during power cycle.
MCU_RESETZ and RESET_REQ_z were being pulled down by default by the MCU preventing boot. Programming the MCU to pull the lines high lets the processor out of reset and we are able to see "C" being printed by the UART bootloader on UART0.
Regards,
Sreenivasa
Hi Board designers
TDA4APE-Q1: Capacitance for MCU_PORz
Please tell me input capacitance of MCU_PORz port?
Here are the steps to determine the input capacitance on a specific IO:
Customer would like to know the exact value of the input capacitance of LVCMOS PIN.
Could you share it ?
The IBIS models have C_pkg (package capacitance, universal min/max for all pins) and C_comp (die capacitance, unique for each buffer type) that can be combined together to get the total capacitance for a pin.
Regards,
Sreenivasa
