- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
Hi guys,
there are ECC aggregator support in TDA4, and we support using ECC to protect the module/RAM/subsystem and bus interconnect. but I'm confused about below question:
1. the the DDR ECC, we need fill the pattern first and it will generate the ECC result(hamming code) if we enable the inline ECC, but which HW component done this calculate ?
2. also we support ECC parity and redumdancy for command&address bus, also the SECDE for data bus, but in bus ECC, is it also generate the Hamming code? if yes, which component done this calculate work?
Br,
Neo
Neo,
1. the the DDR ECC, we need fill the pattern first and it will generate the ECC result(hamming code) if we enable the inline ECC, but which HW component done this calculate ?
The advantage if inline ECC is that no additional HW needed. SPL (Software needs to fill the pattern first before enabling Inline-ECC)
The above lines from TRM.
2. also we support ECC parity and redumdancy for command&address bus, also the SECDE for data bus, but in bus ECC, is it also generate the Hamming code? if yes, which component done this calculate work?
All of that is covered under inline-ECC.
If no further questions please click on verify answer.
- Keerthy
Thanks Keerthy,
But above inline ECC is for SDRAM, the memory, I still confused about the ECC in system interconnect, as below shown, how the system interconnect achieve the ECC?
BR,
Neo
