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TDA4VM: Rgmii_tx clk of macport 5 is always 2.5MHz in 100M eth mode

jeffreysundts
Intellectual 460 points
Part Number: TDA4VM

Hi all,

When we use psdk 7.2 in our customed board, Ethernet can be applied properly except for the macport which is connected with rgmii5. As the result of Rgmii5_tx_clk is in 2.5MHz, the phy can be linked up but no data packages can be send to the cooresponding macport. we have checked that there is no difference between other available 100M rgmii and rgmii5. Also we read-back checked the pinmux registers, the result is same as the configuration we have make as below.

So, could you please help me to solve the problem, and i wonder if there is conflict configuration for the pin below in psdk.

thanks

  • 0
    TI__Mastermind 37435 points

    Hi,

    Sorry for the delay. Let me take a look. Port5 is not enabled in the EVM so I cannot check physically, but there shouldn't be an issue with the driver.

    Are you able to receive packets on Port 5 ?

    Can you share your bootlog and EthFW output ?

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    We can not receive the packets on PORT5. The boot log and ethfw is attached below. Also I want to ask, if I can set macport 5 in rgmii 100M mode in uboot, so that I can check if the rgmii tx_clk is 25Mhz before cpsw init; if  that is the case. it means that the cpsw init make macport in wrong speed mode.

    8475.ethfw.txt 
    root@TDA4-Board:/opt/vision_apps# [MCU2_0]   4597.598817 s: CIO: Init ... Done !!!
[MCU2_0]   4597.598894 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_0]   4597.598935 s: APP: Init ... !!!
[MCU2_0]   4597.598954 s: SCICLIENT: Init ... !!!
[MCU2_0]   4597.600104 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
[MCU2_0]   4597.600155 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_0]   4597.600180 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]   4597.600204 s: SCICLIENT: Init ... Done !!!
[MCU2_0]   4597.600225 s: UDMA: Init ... !!!
[MCU2_0]   4597.610546 s: UDMA: Init ... Done !!!
[MCU2_0]   4597.610602 s: MEM: Init ... !!!
[MCU2_0]   4597.610642 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2400000 of size 8388608 bytes !!!
[MCU2_0]   4597.610702 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 131072 bytes !!!
[MCU2_0]   4597.610748 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce000000 of size 65536 bytes !!!
[MCU2_0]   4597.610791 s: MEM: Init ... Done !!!
[MCU2_0]   4597.610810 s: IPC: Init ... !!!
[MCU2_0]   4597.610843 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]   4597.610880 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]   4608.112198 s: IPC: HLOS is ready !!!
[MCU2_0]   4608.123957 s: IPC: Init ... Done !!!
[MCU2_0]   4608.124019 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]   4608.605057 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]   4608.605106 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]   4608.606749 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]   4608.606820 s: ETHFW: Init ... !!!
[MCU2_0]   4608.617712 s: ==========RGMII3 RXD0============AF28  is 00050004
[MCU2_0]   4608.617796 s: =================================RGMII4 RXD0============AE29  is 00050004
[MCU2_0]   4608.617864 s: =================================RGMII6 RXD0============W25   is 00050000
[MCU2_0]   4608.641469 s: ==============================CPSW_9G=================================
[MCU2_0]   4608.641544 s: Date is Apr 13 2021, Time is 14:30:48
[MCU2_0]   4608.641575 s: File is enet_mcm.c, Func is EnetMcm_open [line@737]
[MCU2_0]   4608.641606 s: CPSW_9G Test on MAIN NAVSS
[MCU2_0]   4608.666125 s: EnetPhy_bindDriver: PHY 3: OUI:000732 Model:33 Ver:00 <-> 'generic' : OK
[MCU2_0]   4608.666488 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'generic' : OK
[MCU2_0]   4608.666777 s: EnetPhy_bindDriver: PHY 2: OUI:000732 Model:33 Ver:00 <-> 'generic' : OK
[MCU2_0]   4608.666851 s: PHY 0 is alive
[MCU2_0]   4608.666878 s: PHY 1 is alive
[MCU2_0]   4608.666898 s: PHY 2 is alive
[MCU2_0]   4608.666916 s: PHY 3 is alive
[MCU2_0]   4608.668832 s: ETHFW: Version   : 0.01.01
[MCU2_0]   4608.668893 s: ETHFW: Build Date: Apr 13, 2021
[MCU2_0]   4608.668918 s: ETHFW: Build Time: 18:18:58
[MCU2_0]   4608.668938 s: ETHFW: Commit SHA:
[MCU2_0]   4608.668962 s: ETHFW: Init ... DONE !!!
[MCU2_0]   4608.668985 s: ETHFW: Remove server Init ... !!!
[MCU2_0]   4608.670489 s: Remote demo device (core : mcu2_0) .....
[MCU2_0]   4608.670555 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]   4608.698919 s: Host MAC address: 70:ff:76:1d:92:c2
[MCU2_0]   4608.725304 s: FVID2: Init ... !!!
[MCU2_0]   4608.725435 s: FVID2: Init ... Done !!!
[MCU2_0]   4608.725485 s: DSS: Init ... !!!
[MCU2_0]   4608.725507 s: DSS: Display type is eDP !!!
[MCU2_0]   4608.725529 s: DSS: SoC init ... !!!
[MCU2_0]   4608.725547 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]   4608.726781 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.726821 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]   4608.728692 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.728729 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]   4608.730013 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.730045 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11
[MCU2_0]   4608.730489 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]   4608.730522 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]   4608.731084 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]   4608.731116 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 [   25.840410] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
clk=1 parent=2
[MCU2_0]   4608.731562 s: SCICLIENT: Sciclient_[   25.854495] j721e-cpsw-virt-mac main_r5fss_cpsw9g_virt_mac0: register_ipv4 rpmsg - fail -5
pmSetModuleClkParent success
[MCU2_0]   4608.731596 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]   4608.750580 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]   4608.750617 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]   4608.751163 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]   4608.751197 s: DSS: SoC init ... Done !!!
[MCU2_0]   4608.751219 s: DSS: Board init ... !!!
[MCU2_0]   4608.751239 s: DSS: Turning on DP_PWR pin for eDP adapters ... !!!
[MCU2_0]   4608.773079 s:
[MCU2_0] CPSW NIMU application, IP address I/F 1: 192.168.1.203
[MCU2_0]   4608.797581 s: EnetPhy_findCommonNwayCaps: PHY 2: no common caps found
[MCU2_0]   4608.797688 s: Cpsw_handleLinkUp: Port 6: Link up: 1-Gbps Full-Duplex
[MCU2_0]   4608.798344 s: DSS: ERROR: Turning on DP_PWR pin for eDP adapters failed !!!
[MCU2_0]   4608.798403 s: DSS: Board init ... Done !!!
[MCU2_0]   4608.819243 s: DSS: Init ... Done !!!
[MCU2_0]   4608.819340 s: VHWA: VPAC Init ... !!!
[MCU2_0]   4608.819365 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]   4608.820166 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.820199 s: VHWA: LDC Init ... !!!
[MCU2_0]   4608.834042 s: VHWA: LDC Init ... Done !!!
[MCU2_0]   4608.834105 s: VHWA: MSC Init ... !!!
[MCU2_0]   4608.876837 s: VHWA: MSC Init ... Done !!!
[MCU2_0]   4608.876897 s: VHWA: NF Init ... !!!
[MCU2_0]   4608.883930 s: VHWA: NF Init ... Done !!!
[MCU2_0]   4608.883986 s: VHWA: VISS Init ... !!!
[MCU2_0]   4608.916368 s: VHWA: VISS Init ... Done !!!
[MCU2_0]   4608.916427 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]   4608.916465 s:  VX_ZONE_INIT:Enabled
[MCU2_0]   4608.916491 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]   4608.916512 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]   4608.917808 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target IPU1-0
[MCU2_0]   4608.918189 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_NF
[MCU2_0]   4608.918586 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_LDC1
[MCU2_0]   4608.918939 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC1
[MCU2_0]   4608.919384 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_MSC2
[MCU2_0]   4608.919788 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VPAC_VISS1
[MCU2_0]   4608.920183 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE1
[MCU2_0]   4608.920660 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE2
[MCU2_0]   4608.921054 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY1
[MCU2_0]   4608.921491 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DISPLAY2
[MCU2_0]   4608.921859 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CSITX
[MCU2_0]   4608.922219 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE3
[MCU2_0]   4608.922634 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE4
[MCU2_0]   4608.922999 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE5
[MCU2_0]   4608.923407 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE6
[MCU2_0]   4608.923799 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE7
[MCU2_0]   4608.924185 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target CAPTURE8
[MCU2_0]   4608.924248 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_0]   4608.924325 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]   4608.926045 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]   4608.938351 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]   4608.938412 s: CSI2RX: Init ... !!!
[MCU2_0]   4608.938432 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]   4608.938948 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.938984 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]   4608.939911 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.939952 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]   4608.940882 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.940913 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]   4608.941422 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.941453 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]   4608.941986 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.945190 s: CSI2RX: Init ... Done !!!
[MCU2_0]   4608.945253 s: CSI2TX: Init ... !!!
[MCU2_0]   4608.945311 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]   4608.945934 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.945967 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]   4608.946981 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.947015 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]   4608.947934 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   4608.951134 s: CSI2TX: Init ... Done !!!
[MCU2_0]   4608.951190 s: ISS: Init ... !!!
[MCU2_0]   4608.951269 s: =======================[SetPinmux,408] PADCONFIG1  :0x50004
[MCU2_0]   4608.951373 s: [SetPinmux,410] PADCONFIG1  :0x50007
[MCU2_0]   4608.951417 s: [SetPinmux,415] PADCONFIG2  :0x50004
[MCU2_0]   4608.951456 s: [SetPinmux,417] PADCONFIG2  :0x50007
[MCU2_0]   4608.951495 s: [SetPinmux,421] PADCONFIG5  :0x50004
[MCU2_0]   4608.951533 s: [SetPinmux,423] PADCONFIG5  :0x50007
[MCU2_0]   4608.951574 s: [SetGPIO,433] Gpio0_Dir01  :0xffffffff
[MCU2_0]   4608.951613 s: [SetGPIO,435] Gpio0_Dir01  :0xfffffffd
[MCU2_0]   4608.951655 s: [SetGPIO,436] Gpio0_OutData01  :0x0
[MCU2_0]   4608.951694 s: [SetGPIO,438] Gpio0_OutData01  :0x2
[MCU2_0]   4608.951734 s: [SetGPIO,439] Gpio0_ClrData01  :0x2
[MCU2_0]   4608.951777 s: [SetGPIO,441] Gpio0_ClrData01  :0x2
[MCU2_0]   4608.951830 s: Found sensor AR0233-UB953_MARS at location 0
[MCU2_0]   4608.951881 s: Found sensor AR0820-UB953_LI at location 1
[MCU2_0]   4608.951929 s: Found sensor GW_AR0233_UYVY at location 2
[MCU2_0]   4608.951975 s: Found sensor AR0220-UB953_MARS at location 3
[MCU2_0]   4608.952022 s: Found sensor AR0820-MAX9295_LI at location 4
[MCU2_0]   4608.952068 s: Found sensor AR0233-MAX9295_MARS at location 5
[MCU2_0]   4608.952120 s: Found sensor AR0233-MAX9295_MARS_MULTI at location 6
[MCU2_0]   4608.952173 s: Found sensor AR0820-MAX9295_LI_MULTI at location 7
[MCU2_0]   4608.952201 s: IssSensor_Init ... Done !!!
[MCU2_0]   4608.952367 s: vissRemoteServer_Init ... Done !!!
[MCU2_0]   4608.952451 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]   4608.952505 s: UDMA Copy: Init ... !!!
[MCU2_0]   4608.960249 s: UDMA Copy: Init ... Done !!!
[MCU2_0]   4608.960333 s: APP: Init ... Done !!!
[MCU2_0]   4608.960358 s: APP: Run ... !!!
[MCU2_0]   4608.960379 s: IPC: Starting echo test ...
[MCU2_0]   4608.963150 s: APP: Run ... Done !!!
[MCU2_0]   4608.963337 s: Create Semaphore success!
[MCU2_0]   4608.963680 s: Create timer success!
[MCU2_0]   4608.963891 s: [Sensor_Gpio_Task,54] Sensor_Gpio_Task Created!
[MCU2_0]   4608.976605 s: EthFw: TimeSync PTP enabled
[MCU2_0]   4608.980071 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0]   4608.980513 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_0]   4608.980753 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_0]   4608.980897 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_0]   4611.397754 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]   4611.401038 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:13, Policer Entry:2
[MCU2_0]   4611.441178 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1 IPv4Addr:192.168.3.120
[MCU2_0]   4611.441494 s: Failed to add Static ARP Entry
[MCU2_0]   4611.441541 s:
[MCU2_0] ================LLI Table entries===========
[MCU2_0]   4611.441571 s:
[MCU2_0] Number of Static ARP Entries: 0
[MCU2_0]   4611.441593 s:
[MCU2_0] SNo.      IP Address         MAC Address
[MCU2_0]   4611.441617 s: ------    -------------      ---------------
[MCU2_0]   4623.545157 s: Function:CpswProxyServer_unregisterMacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:92:c1, FlowIdx:172, FlowIdOffset:0
[MCU2_0]   4623.673709 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6, MacAddress:70:c:29:26:74:13, FlowIdx:172, FlowIdxOffset:0
[MCU2_0]   4623.677009 s: Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:13, Policer Entry:2
[MCU2_0]   4623.686419 s: Function:CpswProxyServer_unregisterIpv4MacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6,IPv4Addr:c0:a8:3:78
[MCU2_0]   4623.686628 s: Failed to add Static ARP Entry
[MCU2_0]   4623.686685 s:
[MCU2_0] ================LLI Table entries===========
[MCU2_0]   4623.686716 s:
[MCU2_0] Number of Static ARP Entries: 0
[MCU2_0]   4623.686741 s:
[MCU2_0] SNo.      IP Address         MAC Address
[MCU2_0]   4623.686765 s: ------    -------------      ---------------
[MCU2_1]   4597.627194 s: CIO: Init ... Done !!!
[MCU2_1]   4597.627276 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[MCU2_1]   4597.627323 s: APP: Init ... !!!
[MCU2_1]   4597.627344 s: SCICLIENT: Init ... !!!
[MCU2_1]   4597.628494 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
[MCU2_1]   4597.628538 s: SCICLIENT: DMSC FW revision 0x14
[MCU2_1]   4597.628564 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]   4597.628589 s: SCICLIENT: Init ... Done !!!
[MCU2_1]   4597.628612 s: UDMA: Init ... !!!
[MCU2_1]   4597.640329 s: UDMA: Init ... Done !!!
[MCU2_1]   4597.640388 s: MEM: Init ... !!!
[MCU2_1]   4597.640430 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d2c00000 of size 16777216 bytes !!!
[MCU2_1]   4597.640491 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3620000 of size 131072 bytes !!!
[MCU2_1]   4597.640542 s: MEM: Created heap (DDR_NON_CACHE_ME, id=5, flags=0x00000000) @ ce010000 of size 67043328 bytes !!!
[MCU2_1]   4597.640591 s: MEM: Init ... Done !!!
[MCU2_1]   4597.640613 s: IPC: Init ... !!!
[MCU2_1]   4597.640645 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_1]   4597.640686 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]   4608.593208 s: IPC: HLOS is ready !!!
[MCU2_1]   4608.604950 s: IPC: Init ... Done !!!
[MCU2_1]   4608.605015 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_1]   4608.605054 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_1]   4608.605085 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]   4608.606625 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]   4608.606688 s: FVID2: Init ... !!!
[MCU2_1]   4608.606775 s: FVID2: Init ... Done !!!
[MCU2_1]   4608.606808 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]   4608.606831 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]   4608.608093 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]   4608.608129 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]   4608.610630 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]   4608.610662 s: VHWA: DOF Init ... !!!
[MCU2_1]   4608.667420 s: VHWA: DOF Init ... Done !!!
[MCU2_1]   4608.667483 s: VHWA: SDE Init ... !!!
[MCU2_1]   4608.682179 s: VHWA: SDE Init ... Done !!!
[MCU2_1]   4608.682240 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]   4608.682271 s: VHWA: Codec: Init ... !!!
[MCU2_1]   4608.682317 s: VHWA: VDEC Init ... !!!
[MCU2_1]   4608.697731 s: VHWA: VDEC Init ... Done !!!
[MCU2_1]   4608.697801 s: VHWA: VENC Init ... !!!
[MCU2_1]   4608.698632 s: MM_ENC_Init: No OCM RAM pool available, fallback to DDR mode for above mp params
[MCU2_1]   4608.756264 s: VHWA: VENC Init ... Done !!!
[MCU2_1]   4608.756360 s: VHWA: Init ... Done !!!
[MCU2_1]   4608.756402 s:  VX_ZONE_INIT:Enabled
[MCU2_1]   4608.756427 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]   4608.756447 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]   4608.757567 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_SDE
[MCU2_1]   4608.757846 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target DMPAC_DOF
[MCU2_1]   4608.758114 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC1
[MCU2_1]   4608.758432 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VDEC2
[MCU2_1]   4608.758703 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC1
[MCU2_1]   4608.758987 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:55] Added target VENC2
[MCU2_1]   4608.759046 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[MCU2_1]   4608.759076 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]   4608.759486 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]   4608.759548 s: UDMA Copy: Init ... !!!
[MCU2_1]   4608.767198 s: UDMA Copy: Init ... Done !!!
[MCU2_1]   4608.767255 s: APP: Init ... Done !!!
[MCU2_1]   4608.767303 s: APP: Run ... !!!
[MCU2_1]   4608.767331 s: IPC: Starting echo test ...
[MCU2_1]   4608.769646 s: APP: Run ... Done !!!
[MCU2_1]   4608.771267 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.]
[MCU2_1]   4608.771400 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.]
[MCU2_1]   4608.771487 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
[MCU2_1]   4608.980075 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P]
[C6x_1 ]   4597.675978 s: CIO: Init ... Done !!!
[C6x_1 ]   4597.676030 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_1 ]   4597.676046 s: APP: Init ... !!!
[C6x_1 ]   4597.676054 s: SCICLIENT: Init ... !!!
[C6x_1 ]   4597.677455 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
[C6x_1 ]   4597.677469 s: SCICLIENT: DMSC FW revision 0x14
[C6x_1 ]   4597.677479 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]   4597.677490 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]   4597.677500 s: UDMA: Init ... !!!
[C6x_1 ]   4597.691817 s: UDMA: Init ... Done !!!
[C6x_1 ]   4597.691842 s: MEM: Init ... !!!
[C6x_1 ]   4597.691857 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d4000000 of size 16777216 bytes !!!
[C6x_1 ]   4597.691876 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]   4597.691893 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d5000000 of size 50331648 bytes !!!
[C6x_1 ]   4597.691910 s: MEM: Init ... Done !!!
[C6x_1 ]   4597.691919 s: IPC: Init ... !!!
[C6x_1 ]   4597.691934 s: IPC: 6 CPUs participating in IPC !!!
[C6x_1 ]   4597.691948 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]   4606.161247 s: IPC: HLOS is ready !!!
[C6x_1 ]   4606.182074 s: IPC: Init ... Done !!!
[C6x_1 ]   4606.182110 s: APP: Syncing with 5 CPUs ... !!!
[C6x_1 ]   4608.605054 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_1 ]   4608.605068 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]   4608.605700 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]   4608.605745 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]   4608.605757 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]   4608.605768 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]   4608.606792 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_1 ]   4608.606814 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]   4608.607215 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]   4608.607234 s: UDMA Copy: Init ... !!!
[C6x_1 ]   4608.629114 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]   4608.629139 s: APP: Init ... Done !!!
[C6x_1 ]   4608.638056 s: APP: Run ... !!!
[C6x_1 ]   4608.638071 s: IPC: Starting echo test ...
[C6x_1 ]   4608.639666 s: APP: Run ... Done !!!
[C6x_1 ]   4608.640143 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[.]
[C6x_1 ]   4608.640183 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ]   4608.770970 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_1 ]   4608.979895 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P]
[C6x_2 ]   4597.723669 s: CIO: Init ... Done !!!
[C6x_2 ]   4597.723709 s: ### CPU Frequency <ORG = 1350000000 Hz>, <NEW = 1350000000 Hz>
[C6x_2 ]   4597.723725 s: APP: Init ... !!!
[C6x_2 ]   4597.723734 s: SCICLIENT: Init ... !!!
[C6x_2 ]   4597.724907 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
[C6x_2 ]   4597.724922 s: SCICLIENT: DMSC FW revision 0x14
[C6x_2 ]   4597.724932 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]   4597.724943 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]   4597.724953 s: UDMA: Init ... !!!
[C6x_2 ]   4597.739025 s: UDMA: Init ... Done !!!
[C6x_2 ]   4597.739050 s: MEM: Init ... !!!
[C6x_2 ]   4597.739067 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ d8000000 of size 16777216 bytes !!!
[C6x_2 ]   4597.739086 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]   4597.739104 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d9000000 of size 50331648 bytes !!!
[C6x_2 ]   4597.739121 s: MEM: Init ... Done !!!
[C6x_2 ]   4597.739130 s: IPC: Init ... !!!
[C6x_2 ]   4597.739146 s: IPC: 6 CPUs participating in IPC !!!
[C6x_2 ]   4597.739160 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]   4606.513699 s: IPC: HLOS is ready !!!
[C6x_2 ]   4606.533018 s: IPC: Init ... Done !!!
[C6x_2 ]   4606.533052 s: APP: Syncing with 5 CPUs ... !!!
[C6x_2 ]   4608.605054 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_2 ]   4608.605068 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]   4608.605717 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]   4608.605760 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]   4608.605771 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]   4608.605781 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]   4608.606794 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C6x_2 ]   4608.606815 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]   4608.607213 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]   4608.607233 s: UDMA Copy: Init ... !!!
[C6x_2 ]   4608.628180 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]   4608.628204 s: APP: Init ... Done !!!
[C6x_2 ]   4608.637106 s: APP: Run ... !!!
[C6x_2 ]   4608.637119 s: IPC: Starting echo test ...
[C6x_2 ]   4608.638467 s: APP: Run ... Done !!!
[C6x_2 ]   4608.638886 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[s] C7X_1[P]
[C6x_2 ]   4608.640157 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ]   4608.770999 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C6x_2 ]   4608.979919 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P]
[C7x_1 ]   4597.784140 s: CIO: Init ... Done !!!
[C7x_1 ]   4597.784165 s: ### CPU Frequency <ORG = 1000000000 Hz>, <NEW = 1000000000 Hz>
[C7x_1 ]   4597.784181 s: APP: Init ... !!!
[C7x_1 ]   4597.784189 s: SCICLIENT: Init ... !!!
[C7x_1 ]   4597.785291 s: SCICLIENT: DMSC FW version [20.8.5--v2020.08b (Terrific Lla]
[C7x_1 ]   4597.785308 s: SCICLIENT: DMSC FW revision 0x14
[C7x_1 ]   4597.785319 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]   4597.785330 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]   4597.785340 s: UDMA: Init ... !!!
[C7x_1 ]   4597.794087 s: UDMA: Init ... Done !!!
[C7x_1 ]   4597.794100 s: MEM: Init ... !!!
[C7x_1 ]   4597.794113 s: MEM: Created heap (DDR_SHARED_MEM, id=0, flags=0x00000004) @ dc000000 of size 268435456 bytes !!!
[C7x_1 ]   4597.794135 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !!!
[C7x_1 ]   4597.794153 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 491520 bytes !!!
[C7x_1 ]   4597.794176 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]   4597.794195 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ ec000000 of size 234881024 bytes !!!
[C7x_1 ]   4597.794214 s: MEM: Init ... Done !!!
[C7x_1 ]   4597.794223 s: IPC: Init ... !!!
[C7x_1 ]   4597.794234 s: IPC: 6 CPUs participating in IPC !!!
[C7x_1 ]   4597.794248 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]   4607.262009 s: IPC: HLOS is ready !!!
[C7x_1 ]   4607.272333 s: IPC: Init ... Done !!!
[C7x_1 ]   4607.272349 s: APP: Syncing with 5 CPUs ... !!!
[C7x_1 ]   4608.605056 s: APP: Syncing with 5 CPUs ... Done !!!
[C7x_1 ]   4608.605074 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]   4608.605348 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]   4608.605372 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]   4608.605385 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]   4608.605395 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]   4608.605694 s:  VX_ZONE_INIT:[tivxInit:71] Initialization Done !!!
[C7x_1 ]   4608.605710 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]   4608.605817 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]   4608.605844 s: APP: Init ... Done !!!
[C7x_1 ]   4608.605868 s: APP: Run ... !!!
[C7x_1 ]   4608.605880 s: IPC: Starting echo test ...
[C7x_1 ]   4608.606395 s: APP: Run ... Done !!!
[C7x_1 ]   4608.638901 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[x] C66X_2[P] C7X_1[s]
[C7x_1 ]   4608.640142 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s]
[C7x_1 ]   4608.771023 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
[C7x_1 ]   4608.979982 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s]
[MCU2_0]   4624.685973 s: Function:CpswProxyServer_registerIpv4MacHandlerCb,HostId:0,Handle:a272dae0,CoreKey:38acb7e6, MacAddress:70:c:29:26:74:13 IPv4Addr:192.168.3.120
[MCU2_0]   4624.686240 s: Failed to add Static ARP Entry
[MCU2_0]   4624.686341 s:
[MCU2_0] ================LLI Table entries===========
[MCU2_0]   4624.686380 s:
[MCU2_0] Number of Static ARP Entries: 0
[MCU2_0]   4624.686403 s:
[MCU2_0] SNo.      IP Address         MAC Address
[MCU2_0]   4624.686428 s: ------    -------------      ---------------
[   35.888399] tlv71033: disabling
    8540.bootlog.txt

    with regards

  • 0 in reply to jeffreysundts
    TI__Mastermind 37435 points

    Hi Jeffrey,

    Can you also dump statistics for CPSW 9G using this script ?

    4846.cpsw_all_reg_print.c 
     
#include <ctype.h>
#include <error.h>
#include <fcntl.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <unistd.h>

#define MEMORY "/dev/mem"

#define CSL_FEXTR(reg, msb, lsb)                                            \
    (((reg) >> (lsb)) & ((((uint32_t)1U) << ((msb) - (lsb) + ((uint32_t)1U))) - ((uint32_t)1U)))

#define CPSW_9G_PORT_NUM        8
#define CPSW_5G_PORT_NUM        4
#define CPSW_2G_PORT_NUM        1

#define CPSW_2G_MAC_PORT_NUM         (1U)
#define CPSW_5G_MAC_PORT_NUM         (4U)
#define CPSW_9G_MAC_PORT_NUM         (8U)

#define ALE_TBLCTL_2G              0x4603E020
#define ALE_TBLW2_2G               0x4603E034
#define ALE_TBLW1_2G               0x4603E038
#define ALE_TBLW0_2G               0x4603E03C

#define ALE_TBLCTL_9G              0x0C03E020
#define ALE_TBLW2_9G               0x0C03E034
#define ALE_TBLW1_9G               0x0C03E038
#define ALE_TBLW0_9G               0x0C03E03C

#define ALE_TABLE_DEPTH_2G         64
#define ALE_TABLE_DEPTH_5G         512
#define ALE_TABLE_DEPTH_9G         1024


#define ALE_ENTRY_EMTPY         0x0
#define ALE_ENTRY_ADDR          0x1
#define ALE_ENTRY_VLAN          0x2
#define ALE_ENTRY_VLAN_ADDR     0x3

#define MCU_CTRLMMR_ENET_CTRL          (0x40F04040)
#define MAIN_CTRLMMR_ENET0_CTRL         (0x00104044)

#define CPSW_MAC_MODE_GMII       (0U)
#define CPSW_MAC_MODE_RMII       (1U)
#define CPSW_MAC_MODE_RGMII      (2U)
#define CPSW_MAC_MODE_SGMII      (3U)
#define CPSW_MAC_MODE_QSGMII     (4U)
#define CPSW_MAC_MODE_QSGMII_SUB (6U)

#define CPSW_RGMII_ID_ENABLED     (0U)
#define CPSW_RGMII_ID_DISABLED    (1U)

#define BOARD_CPSW2G_MAC_MODE (CPSW_MAC_MODE_RGMII)
#define BOARD_CPSW2G_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW5G_PORT0_MAC_MODE (CPSW_MAC_MODE_QSGMII)
#define BOARD_CPSW5G_PORT0_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW5G_PORT1_MAC_MODE (CPSW_MAC_MODE_QSGMII_SUB)
#define BOARD_CPSW5G_PORT1_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW5G_PORT2_MAC_MODE (CPSW_MAC_MODE_QSGMII_SUB)
#define BOARD_CPSW5G_PORT2_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW5G_PORT3_MAC_MODE (CPSW_MAC_MODE_QSGMII_SUB)
#define BOARD_CPSW5G_PORT3_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW9G_PORT0_MAC_MODE (CPSW_MAC_MODE_RGMII)
#define BOARD_CPSW9G_PORT0_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW9G_PORT1_MAC_MODE (CPSW_MAC_MODE_RGMII)
#define BOARD_CPSW9G_PORT1_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW9G_PORT2_MAC_MODE (CPSW_MAC_MODE_RGMII)
#define BOARD_CPSW9G_PORT2_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW9G_PORT3_MAC_MODE (CPSW_MAC_MODE_RGMII)
#define BOARD_CPSW9G_PORT3_RGMII_ID (CPSW_RGMII_ID_DISABLED)

#define BOARD_CPSW9G_PORT7_MAC_MODE (CPSW_MAC_MODE_RMII)

#define CPSW5G_BASE_ADDR                            (0x0C000000)
#define CPSW9G_BASE_ADDR                            (0x0C000000)
#define CPSW2G_BASE_ADDR                            (0x46000000)

#define CSL_CPSW_NU_CPSW_NU_ETH_PN_MAC_CONTROL_REG                      (0x00022330U)
#define CSL_CPSW_NU_CPSW_NU_ETH_PN_MAC_STATUS_REG                       (0x00022334U)

#define CTRLMMR_BASE_OFFSET                     (0x100000)
#define ENET1_CTRL_OFFSET                       (0x4044)
#define ENET2_CTRL_OFFSET                       (0x4048)
#define ENET3_CTRL_OFFSET                       (0x404C)
#define ENET4_CTRL_OFFSET                       (0x4050)

#define CPSW_CLKSEL_OFFSET                      (0x8090)

#define CPSW_CONTROL_REG_OFFSET                 (0x20004)

#define RGMII1_STATUS_REG_OFFSET                (0x30)
#define RGMII2_STATUS_REG_OFFSET                (0x34)
#define RGMII3_STATUS_REG_OFFSET                (0x38)
#define RGMII4_STATUS_REG_OFFSET                (0x3C)

#define CPSW_PN_MAC_CONTROL_REG_OFFSET          (0x22330)

/* PN_MAC_CONTROL_REG */
#define MAC_CONTROL_REG_FULLDUPLEX_SHIFT     (0x00000000U)
#define MAC_CONTROL_REG_LOOPBACK_SHIFT       (0x00000001U)
#define MAC_CONTROL_REG_MTEST_SHIFT          (0x00000002U)
#define MAC_CONTROL_REG_RX_FLOW_EN_SHIFT     (0x00000003U)
#define MAC_CONTROL_REG_TX_FLOW_EN_SHIFT     (0x00000004U)
#define MAC_CONTROL_REG_GMII_EN_SHIFT        (0x00000005U)
#define MAC_CONTROL_REG_TX_PACE_SHIFT        (0x00000006U)
#define MAC_CONTROL_REG_GIG_SHIFT            (0x00000007U)
#define MAC_CONTROL_REG_TX_SHORT_GAP_ENABLE_SHIFT (0x0000000AU)
#define MAC_CONTROL_REG_CMD_IDLE_SHIFT       (0x0000000BU)
#define MAC_CONTROL_REG_CRC_TYPE_SHIFT       (0x0000000CU)
#define MAC_CONTROL_REG_IFCTL_A_SHIFT        (0x0000000FU)
#define MAC_CONTROL_REG_IFCTL_B_SHIFT        (0x00000010U)
#define MAC_CONTROL_REG_GIG_FORCE_SHIFT      (0x00000011U)
#define MAC_CONTROL_REG_CTL_EN_SHIFT         (0x00000012U)
#define MAC_CONTROL_REG_EXT_RX_FLOW_EN_SHIFT (0x00000013U)
#define MAC_CONTROL_REG_EXT_TX_FLOW_EN_SHIFT (0x00000014U)
#define MAC_CONTROL_REG_TX_SHORT_GAP_LIM_EN_SHIFT (0x00000015U)
#define MAC_CONTROL_REG_RX_CEF_EN_SHIFT      (0x00000016U)
#define MAC_CONTROL_REG_RX_CSF_EN_SHIFT      (0x00000017U)
#define MAC_CONTROL_REG_RX_CMF_EN_SHIFT      (0x00000018U)

/* PN_MAC_STATUS_REG */
#define MAC_STATUS_REG_TX_FLOW_ACT_SHIFT     (0x00000000U)
#define MAC_STATUS_REG_RX_FLOW_ACT_SHIFT     (0x00000001U)
#define MAC_STATUS_REG_EXT_FULLDUPLEX_SHIFT  (0x00000003U)
#define MAC_STATUS_REG_EXT_GIG_SHIFT         (0x00000004U)
#define MAC_STATUS_REG_EXT_TX_FLOW_EN_SHIFT  (0x00000005U)
#define MAC_STATUS_REG_EXT_RX_FLOW_EN_SHIFT  (0x00000006U)
#define MAC_STATUS_REG_RX_PFC_FLOW_ACT_SHIFT (0x00000008U)
#define MAC_STATUS_REG_TX_PFC_FLOW_ACT_SHIFT (0x00000010U)
#define MAC_STATUS_REG_TORF_PRI_SHIFT        (0x00000018U)
#define MAC_STATUS_REG_TORF_SHIFT            (0x0000001BU)
#define MAC_STATUS_REG_TX_IDLE_SHIFT         (0x0000001CU)
#define MAC_STATUS_REG_P_IDLE_SHIFT          (0x0000001DU)
#define MAC_STATUS_REG_E_IDLE_SHIFT          (0x0000001EU)
#define MAC_STATUS_REG_IDLE_SHIFT            (0x0000001FU)

/*! Macro to get bit at given bit position  */
#define ENET_GET_BIT(val, n)            ((val & (1 << n)) >> n)

int      fd;

unsigned page_size, mapped_size, offset_in_page;
void *   map_base, *virt_addr;
int      fd;

uint32_t mmio_read_32(unsigned long int addr);
void mmio_write_32(unsigned long int addr, uint32_t value);

static void unmap_address(void)
{
    if (munmap(map_base, mapped_size) == -1)
        fprintf(stderr, "munmap");
    close(fd);
}

static int map_address(off_t target)
{
    unsigned int width = 8 * sizeof(uint64_t);

    fd = open(MEMORY, (O_RDWR | O_SYNC));
    if (fd < 0)
    {
        fprintf(stderr, "Could not open %s!\n", MEMORY);
        return -5;
    }

    mapped_size = page_size = getpagesize();
    offset_in_page          = (unsigned)target & (page_size - 1);
    if (offset_in_page + width > page_size)
    {
        /*
         * This access spans pages.
         * Must map two pages to make it possible:
         */
        mapped_size *= 2;
    }
    map_base = mmap(NULL, mapped_size, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, target & ~(off_t)(page_size - 1));
    if (map_base == MAP_FAILED)
    {
        fprintf(stderr, "Map fail\n");
        return -1;
    }

    virt_addr = (char *)map_base + offset_in_page;
    return 0;
}

static uint64_t read_reg(int width)
{
    uint64_t read_result = 0x0;

    switch (width)
    {
        case 8:
            read_result = *(volatile uint8_t *)virt_addr;
            break;
        case 16:
            read_result = *(volatile uint16_t *)virt_addr;
            break;
        case 32:
            read_result = *(volatile uint32_t *)virt_addr;
            break;
        case 64:
            read_result = *(volatile uint64_t *)virt_addr;
            break;
        default:
            fprintf(stderr, "bad width");
    }

    return read_result;
}

static void write_reg(int width, uint64_t writeval)
{
    switch (width)
    {
        case 8:
            *(volatile uint8_t *)virt_addr = writeval;
            break;
        case 16:
            *(volatile uint16_t *)virt_addr = writeval;
            break;
        case 32:
            *(volatile uint32_t *)virt_addr = writeval;
            break;
        case 64:
            *(volatile uint64_t *)virt_addr = writeval;
            break;
        default:
            fprintf(stderr, "bad width");
    }
}

uint32_t mmio_read_32(unsigned long int addr)
{
    uint32_t v = 0;
    int      r;

    r = map_address(addr);
    if (r)
        return 0;
    v = read_reg(32);
    unmap_address();
    return v;
}

void mmio_write_32(unsigned long int addr, uint32_t value)
{
    int r;

    r = map_address(addr);
    if (r)
        return;
    write_reg(32, value);
    unmap_address();
}

void Cpsw_ng_PrintMACCfg_local(int portBaseAddr, int cpsw2gFlag)
{
    int macCtrl, macStatus;

    macCtrl   = mmio_read_32(portBaseAddr + CSL_CPSW_NU_CPSW_NU_ETH_PN_MAC_CONTROL_REG);
    macStatus = mmio_read_32(portBaseAddr + CSL_CPSW_NU_CPSW_NU_ETH_PN_MAC_STATUS_REG);

    printf("MAC Control \n");
    printf(" FULLDUPLEX          = %d \n", ENET_GET_BIT(macCtrl, 0U));
    printf(" LOOPBACK            = %d \n", ENET_GET_BIT(macCtrl, 1U));
    printf(" MTEST               = %d \n", ENET_GET_BIT(macCtrl, 2U));
    printf(" RX_FLOW_EN          = %d \n", ENET_GET_BIT(macCtrl, 3U));
    printf(" TX_FLOW_EN          = %d \n", ENET_GET_BIT(macCtrl, 4U));
    printf(" GMII_EN             = %d \n", ENET_GET_BIT(macCtrl, 5U));
    printf(" TX_PACE             = %d \n", ENET_GET_BIT(macCtrl, 6U));
    printf(" GIG                 = %d \n", ENET_GET_BIT(macCtrl, 7U));
    if (0U == cpsw2gFlag)
    {
        printf(" XGIG                 = %d \n", ENET_GET_BIT(macCtrl, 8U));
    }
    printf(" TX_SHORT_GAP_ENABLE = %d \n", ENET_GET_BIT(macCtrl, 10U));
    printf(" CMD_IDLE            = %d \n", ENET_GET_BIT(macCtrl, 11U));
    printf(" CRC_TYPE            = %d \n", ENET_GET_BIT(macCtrl, 12U));
    if (0U == cpsw2gFlag)
    {
        printf(" XGMII EN            = %d \n", ENET_GET_BIT(macCtrl, 13U));
    }
    printf(" IFCTL_A             = %d \n", ENET_GET_BIT(macCtrl, 15U));
    printf(" IFCTL_B             = %d \n", ENET_GET_BIT(macCtrl, 16U));
    printf(" GIG_FORCE           = %d \n", ENET_GET_BIT(macCtrl, 17U));
    printf(" EXT CTL_EN          = %d \n", ENET_GET_BIT(macCtrl, 18U));
    printf(" EXT_RX_FLOW_EN      = %d \n", ENET_GET_BIT(macCtrl, 19U));
    printf(" EXT_TX_FLOW_EN      = %d \n", ENET_GET_BIT(macCtrl, 20U));
    printf(" TX_SHORT_GAP_LIM_EN = %d \n", ENET_GET_BIT(macCtrl, 21U));
    printf(" RX_CEF_EN           = %d \n", ENET_GET_BIT(macCtrl, 22U));
    printf(" RX_CSF_EN           = %d \n", ENET_GET_BIT(macCtrl, 23U));
    printf(" RX_CMF_EN           = %d \n", ENET_GET_BIT(macCtrl, 24U));
    if (0U == cpsw2gFlag)
    {
        printf(" EXT_EN_XGIG         = %d \n", ENET_GET_BIT(macCtrl, 25U));
    }

    /* PN_MAC_STATUS_REG */
    printf("MAC Status \n");
    printf(" TX_FLOW_ACT     = %d \n", ENET_GET_BIT(macStatus, 0U));
    printf(" RX_FLOW_ACT     = %d \n", ENET_GET_BIT(macStatus, 1U));
    printf(" EXT_FULLDUPLEX  = %d \n", ENET_GET_BIT(macStatus, 3U));
    printf(" EXT_GIG         = %d \n", ENET_GET_BIT(macStatus, 4U));
    printf(" EXT_TX_FLOW_EN  = %d \n", ENET_GET_BIT(macStatus, 5U));
    printf(" EXT_RX_FLOW_EN  = %d \n", ENET_GET_BIT(macStatus, 6U));
    printf(" RX_PFC_FLOW_ACT = %d \n", CSL_FEXTR(macStatus, 15, 8));
    printf(" TX_PFC_FLOW_ACT = %d \n", CSL_FEXTR(macStatus, 23, 16));
    printf(" TORF_PRI        = %d \n", CSL_FEXTR(macStatus, 26, 24));
    printf(" TORF            = %d \n", ENET_GET_BIT(macStatus, 27U));
    printf(" MAC_TX_IDLE     = %d \n", ENET_GET_BIT(macStatus, 28U));
    printf(" P_IDLE          = %d \n", ENET_GET_BIT(macStatus, 29U));
    printf(" E_IDLE          = %d \n", ENET_GET_BIT(macStatus, 30U));
    printf(" IDLE            = %d \n", ENET_GET_BIT(macStatus, 31U));
}

void Cpsw2g_PrintMACCfg()
{
    int portBaseAddr = CPSW2G_BASE_ADDR + (1U * 0x1000);
    printf("CPSW2G MAC Port %d \n",1U);
    Cpsw_ng_PrintMACCfg_local(portBaseAddr, 1U);
}

void Cpsw5g_PrintMACCfg()
{
    int i, portNum;
    int portBaseAddr;

    for (portNum = 1; portNum < CPSW_5G_MAC_PORT_NUM; portNum++)
    {
        portBaseAddr = CPSW5G_BASE_ADDR + (portNum * 0x1000);
        printf("CPSW5G Port %d \n",portNum);
        Cpsw_ng_PrintMACCfg_local(portBaseAddr, 0U);
    }
}

void Cpsw9g_PrintMACCfg()
{
    int i, portNum;
    int portBaseAddr;

    for (portNum = 1; portNum < CPSW_9G_MAC_PORT_NUM; portNum++)
    {
        portBaseAddr = CPSW5G_BASE_ADDR + (portNum * 0x1000);
        printf("CPSW5G Port %d \n",portNum);
        Cpsw_ng_PrintMACCfg_local(portBaseAddr, 0U);
    }
}

void Cpsw5g_printKeyMiiRegs()
{
    uint32_t regVal;
    regVal   = mmio_read_32(CTRLMMR_BASE_OFFSET + ENET1_CTRL_OFFSET);
    printf("CTRLMMR_ENET1_CTRL : 0x%x\n", regVal);

    regVal   = mmio_read_32(CTRLMMR_BASE_OFFSET + ENET2_CTRL_OFFSET);
    printf("CTRLMMR_ENET2_CTRL : 0x%x\n", regVal);

    regVal   = mmio_read_32(CTRLMMR_BASE_OFFSET + ENET3_CTRL_OFFSET);
    printf("CTRLMMR_ENET3_CTRL : 0x%x\n", regVal);

    regVal   = mmio_read_32(CTRLMMR_BASE_OFFSET + ENET4_CTRL_OFFSET);
    printf("CTRLMMR_ENET4_CTRL : 0x%x\n", regVal);

    regVal   = mmio_read_32(CTRLMMR_BASE_OFFSET + CPSW_CLKSEL_OFFSET);
    printf("CTRLMMR_CPSW_CLKSEL : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + RGMII1_STATUS_REG_OFFSET);
    printf("RGMII1_STATUS : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + RGMII2_STATUS_REG_OFFSET);
    printf("RGMII2_STATUS : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + RGMII3_STATUS_REG_OFFSET);
    printf("RGMII3_STATUS : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + RGMII4_STATUS_REG_OFFSET);
    printf("RGMII5_STATUS : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + CPSW_PN_MAC_CONTROL_REG_OFFSET);
    printf("MAC_CONTROL_1 : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + CPSW_PN_MAC_CONTROL_REG_OFFSET + 0x1000);
    printf("MAC_CONTROL_2 : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + CPSW_PN_MAC_CONTROL_REG_OFFSET + 0x2000);
    printf("MAC_CONTROL_3 : 0x%x\n", regVal);

    regVal   = mmio_read_32(CPSW5G_BASE_ADDR + CPSW_PN_MAC_CONTROL_REG_OFFSET + 0x3000);
    printf("MAC_CONTROL_4 : 0x%x\n", regVal);

}

int Cpsw_getMacMod(int enetCtrl)
{
    return (enetCtrl & 0x7);
}

int Cpsw_getRgmiiId(int enetCtrl)
{
    return ((enetCtrl >> 4) & 0x1);
}

char* Cpsw_printRgmiiIdCfg(int rgmiiIdVal)
{
    if (CPSW_RGMII_ID_DISABLED == rgmiiIdVal)
    {
        return ("RGMII-ID:Disabled");
    }
    else
    {
        return("RGMII-ID:Enabled");
    }
}

char* Cpsw_printMacMode(int mode)
{
    if (CPSW_MAC_MODE_GMII == mode)
    {
        return("Mode: GMII");
    }
    else if (CPSW_MAC_MODE_RMII == mode)
    {
        return("Mode: RMII");
    }
    else if (CPSW_MAC_MODE_RGMII == mode)
    {
        return("Mode: RGMII");
    }
    else if (CPSW_MAC_MODE_SGMII == mode)
    {
        return("Mode: SGMII");
    }
    else if (CPSW_MAC_MODE_QSGMII == mode)
    {
        return("Mode: QSGMII");
    }
    else if (CPSW_MAC_MODE_QSGMII_SUB == mode)
    {
        return("Mode: QSGMII_SUB");
    }
    else
    {
        return("ERROR!");
    }
}

void Cpsw_printCfg(int portNum, int mode, int rgmiiIdVal)
{
    if (2U == mode)
    {
        printf("Port %d: %s, %s \n",
                portNum, Cpsw_printMacMode(mode), Cpsw_printRgmiiIdCfg(rgmiiIdVal));
    }
    else
    {
        printf("Port %d: %s\n",portNum, Cpsw_printMacMode(mode));
    }
}

void Cpsw2g_PrintEnetCtrl()
{
    int enetCtrl;
    int modeVal, rgmiiIdVal;

    printf("\n");
    printf("==============================\n");
    printf("     CPSW2G MAC Mode Config   \n");
    printf("==============================\n");

    enetCtrl = mmio_read_32(MCU_CTRLMMR_ENET_CTRL);
    Cpsw_printCfg(0, Cpsw_getMacMod(enetCtrl), Cpsw_getRgmiiId(enetCtrl));
}

void Cpsw5g_PrintEnetCtrl()
{
    int enetCtrl;
    int portNum;

    printf("\n");
    printf("==============================\n");
    printf("     CPSW5G MAC Mode Config   \n");
    printf("==============================\n");

    for (portNum = 0; portNum < CPSW_5G_PORT_NUM; portNum++)
    {
        enetCtrl = mmio_read_32(MAIN_CTRLMMR_ENET0_CTRL + (portNum * 0x04));
        Cpsw_printCfg(portNum, Cpsw_getMacMod(enetCtrl), Cpsw_getRgmiiId(enetCtrl));
    }
}

void Cpsw9g_PrintEnetCtrl()
{
    int enetCtrl;
    int portNum;

    printf("\n");
    printf("==============================\n");
    printf("     CPSW9G MAC Mode Config   \n");
    printf("==============================\n");

    for (portNum = 0; portNum < CPSW_9G_PORT_NUM; portNum++)
    {
        enetCtrl = mmio_read_32(MAIN_CTRLMMR_ENET0_CTRL + (portNum * 0x04));
        Cpsw_printCfg(portNum, Cpsw_getMacMod(enetCtrl), Cpsw_getRgmiiId(enetCtrl));
    }
}

void Cpsw_matchEnetCntlCfg(int expMacMode,
                       int currMacMode,
                       int expRgmiiId,
                       int currRgmiiId)

{
    if (expMacMode == currMacMode)
    {
        if ((expMacMode == CPSW_MAC_MODE_RGMII) && (expRgmiiId == currRgmiiId))
        {
            printf("   Config Matches\n");
        }
        else
        {
            printf("   Config Matches\n");
        }
    }
    else
    {
        if (expMacMode != currMacMode)
        {
            printf("   ERROR: Expected: %s, Actual: %s \n",
                            Cpsw_printMacMode(expMacMode), Cpsw_printMacMode(currMacMode));
        }
        if ((expRgmiiId != currRgmiiId) && (expMacMode == CPSW_MAC_MODE_RGMII))
        {
            printf("   ERROR: Expected: %s, Actual: %s \n",
                          Cpsw_printRgmiiIdCfg(expRgmiiId),
                          Cpsw_printRgmiiIdCfg(currRgmiiId));
        }
    }
}

void Board_Cpsw5g_VerifyEnetCtrl()
{
    int currMacMode, currRgmiiId, enetCtrl, portNum;

    for (portNum = 0; portNum < CPSW_5G_PORT_NUM; portNum++)
    {
        enetCtrl = mmio_read_32(MAIN_CTRLMMR_ENET0_CTRL + (portNum * 0x04));
        currMacMode = Cpsw_getMacMod(enetCtrl);
        currRgmiiId = Cpsw_getRgmiiId(enetCtrl);

        printf("CPSW9G Port %d \n",portNum);
        if (0U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW5G_PORT0_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW5G_PORT0_RGMII_ID,
                                   currRgmiiId);
        }
        else if (1U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW5G_PORT1_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW5G_PORT1_RGMII_ID,
                                   currRgmiiId);
        }
        else if (2U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW5G_PORT2_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW5G_PORT2_RGMII_ID,
                                   currRgmiiId);
        }
        else if (3U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW5G_PORT3_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW5G_PORT3_RGMII_ID,
                                   currRgmiiId);
        }
        else
        {
            printf("   Not configured \n");
        }
    }
    printf("\n");
}

void Board_Cpsw9g_VerifyEnetCtrl()
{
    int currMacMode, currRgmiiId, enetCtrl, portNum;

    for (portNum = 0; portNum < CPSW_9G_PORT_NUM; portNum++)
    {
        enetCtrl = mmio_read_32(MAIN_CTRLMMR_ENET0_CTRL + (portNum * 0x04));
        currMacMode = Cpsw_getMacMod(enetCtrl);
        currRgmiiId = Cpsw_getRgmiiId(enetCtrl);

        printf("CPSW9G Port %d \n",portNum);
        if (0U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW9G_PORT0_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW9G_PORT0_RGMII_ID,
                                   currRgmiiId);
        }
        else if (1U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW9G_PORT1_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW9G_PORT1_RGMII_ID,
                                   currRgmiiId);
        }
        else if (2U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW9G_PORT2_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW9G_PORT2_RGMII_ID,
                                   currRgmiiId);
        }
        else if (3U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW9G_PORT3_MAC_MODE,
                                   currMacMode,
                                   BOARD_CPSW9G_PORT3_RGMII_ID,
                                   currRgmiiId);
        }
        else if (7U == portNum)
        {
            Cpsw_matchEnetCntlCfg(BOARD_CPSW9G_PORT7_MAC_MODE,
                                   currMacMode,
                                   0U, /* don't care */
                                   currRgmiiId);
        }
        else
        {
            printf("   Not configured \n");
        }
    }
    printf("\n");
}

void Board_Cpsw2g_VerifyEnetCtrl()
{
    int currMacMode, currRgmiiId, enetCtrl;

    enetCtrl = mmio_read_32(MCU_CTRLMMR_ENET_CTRL);
    currMacMode = Cpsw_getMacMod(enetCtrl);
    currRgmiiId = Cpsw_getRgmiiId(enetCtrl);

    printf("CPSW2G Port 0 \n");
    Cpsw_matchEnetCntlCfg(BOARD_CPSW2G_MAC_MODE,
                           currMacMode,
                           BOARD_CPSW2G_RGMII_ID,
                           currRgmiiId);
    printf("\n");
}

void Board_VerifyEnetCtrlCfg_J721E_EVM()
{

    printf("\n");
    printf("==============================\n");
    printf("  BOARD Verify ENET CTRL  \n");
    printf("==============================\n");
    Board_Cpsw2g_VerifyEnetCtrl();
    Board_Cpsw9g_VerifyEnetCtrl();
}

void Board_VerifyEnetCtrlCfg_J7200_EVM()
{

    printf("\n");
    printf("==============================\n");
    printf("  BOARD Verify ENET CTRL  \n");
    printf("==============================\n");
    Board_Cpsw2g_VerifyEnetCtrl();
    Board_Cpsw5g_VerifyEnetCtrl();
}

void Cpsw_PrintEnetCtrlCfg_J721E()
{
    Cpsw2g_PrintEnetCtrl();
    Cpsw9g_PrintEnetCtrl();
}

void Cpsw_PrintEnetCtrlCfg_J7200()
{
    Cpsw2g_PrintEnetCtrl();
    Cpsw5g_PrintEnetCtrl();
}

void cpsw_print_stat_with_index_nonzero(char* regName, uint32_t portnum, uint32_t regIdx, unsigned long int regAddr)
{
    uint32_t regVal = mmio_read_32(regAddr);
    if (0 != regVal)
    {
        printf("STAT_%d_%s[%d]= %x\n", portnum, regName, regIdx, regVal);
    }
}

void cpsw_print_stat_nonzero(char* regName, uint32_t portnum, unsigned long int regAddr)
{
    uint32_t regVal = mmio_read_32(regAddr);
    if (0 != regVal)
    {
        printf("STAT_%d_%s= %x\n",portnum, regName, regVal);
    }
}

void cpsw_2g_statsprint_nonzero()
{
    uint32_t i, regAddr, portnum;

    printf("          STATS          \n");

    portnum = 0;
    printf("--------------------------------\n");
    printf("          PORT%d STATS          \n",portnum);
    printf("--------------------------------\n");
    cpsw_print_stat_nonzero("RXGOODFRAMES              ", portnum, (0x4603A000U));
    cpsw_print_stat_nonzero("RXBROADCASTFRAMES         ", portnum, (0x4603A004U));
    cpsw_print_stat_nonzero("RXMULTICASTFRAMES         ", portnum, (0x4603A008U));
    cpsw_print_stat_nonzero("RXCRCERRORS               ", portnum, (0x4603A010U));
    cpsw_print_stat_nonzero("RXOVERSIZEDFRAMES         ", portnum, (0x4603A018U));
    cpsw_print_stat_nonzero("RXUNDERSIZEDFRAMES        ", portnum, (0x4603A020U));
    cpsw_print_stat_nonzero("RXFRAGMENTS               ", portnum, (0x4603A024U));
    cpsw_print_stat_nonzero("ALE_DROP                  ", portnum, (0x4603A028U));
    cpsw_print_stat_nonzero("ALE_OVERRUN_DROP          ", portnum, (0x4603A02CU));
    cpsw_print_stat_nonzero("RXOCTETS                  ", portnum, (0x4603A030U));
    cpsw_print_stat_nonzero("TXGOODFRAMES              ", portnum, (0x4603A034U));
    cpsw_print_stat_nonzero("TXBROADCASTFRAMES         ", portnum, (0x4603A038U));
    cpsw_print_stat_nonzero("TXMULTICASTFRAMES         ", portnum, (0x4603A03CU));
    cpsw_print_stat_nonzero("TXOCTETS                  ", portnum, (0x4603A064U));
    cpsw_print_stat_nonzero("OCTETFRAMES64             ", portnum, (0x4603A068U));
    cpsw_print_stat_nonzero("OCTETFRAMES65T127         ", portnum, (0x4603A06CU));
    cpsw_print_stat_nonzero("OCTETFRAMES128T255        ", portnum, (0x4603A070U));
    cpsw_print_stat_nonzero("OCTETFRAMES256T511        ", portnum, (0x4603A074U));
    cpsw_print_stat_nonzero("OCTETFRAMES512T1023       ", portnum, (0x4603A078U));
    cpsw_print_stat_nonzero("OCTETFRAMES1024TUP        ", portnum, (0x4603A07CU));
    cpsw_print_stat_nonzero("NETOCTETS                 ", portnum, (0x4603A080U));
    cpsw_print_stat_nonzero("RX_BOTTOM_OF_FIFO_DROP    ", portnum, (0x4603A084U));
    cpsw_print_stat_nonzero("PORTMASK_DROP             ", portnum, (0x4603A088U));
    cpsw_print_stat_nonzero("RX_TOP_OF_FIFO_DROP       ", portnum, (0x4603A08CU));
    cpsw_print_stat_nonzero("ALE_RATE_LIMIT_DROP       ", portnum, (0x4603A090U));
    cpsw_print_stat_nonzero("ALE_VID_INGRESS_DROP      ", portnum, (0x4603A094U));
    cpsw_print_stat_nonzero("ALE_DA_EQ_SA_DROP         ", portnum, (0x4603A098U));
    cpsw_print_stat_nonzero("ALE_BLOCK_DROP            ", portnum, (0x4603A09CU));
    cpsw_print_stat_nonzero("ALE_SECURE_DROP           ", portnum, (0x4603A0A0U));
    cpsw_print_stat_nonzero("ALE_AUTH_DROP             ", portnum, (0x4603A0A4U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI              ", portnum, (0x4603A0A8U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI_BCNT         ", portnum, (0x4603A0ACU));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT              ", portnum, (0x4603A0B0U));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT_BCNT         ", portnum, (0x4603A0B4U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD              ", portnum, (0x4603A0B8U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD_BCNT         ", portnum, (0x4603A0BCU));
    cpsw_print_stat_nonzero("ALE_POL_MATCH             ", portnum, (0x4603A0C0U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_RED         ", portnum, (0x4603A0C4U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_YELLOW      ", portnum, (0x4603A0C8U));
    cpsw_print_stat_nonzero("TX_MEMORY_PROTECT_ERROR   ", portnum, (0x4603A17CU));

    portnum = 1;
    printf("--------------------------------\n");
    printf("          PORT%d STATS          \n",portnum);
    printf("--------------------------------\n");
    cpsw_print_stat_nonzero("RXGOODFRAMES              ", portnum, (0x4603A200U));
    cpsw_print_stat_nonzero("RXBROADCASTFRAMES         ", portnum, (0x4603A204U));
    cpsw_print_stat_nonzero("RXMULTICASTFRAMES         ", portnum, (0x4603A208U));
    cpsw_print_stat_nonzero("RXPAUSEFRAMES             ", portnum, (0x4603A20CU));
    cpsw_print_stat_nonzero("RXCRCERRORS               ", portnum, (0x4603A210U));
    cpsw_print_stat_nonzero("RXALIGNCODEERRORS         ", portnum, (0x4603A214U));
    cpsw_print_stat_nonzero("RXOVERSIZEDFRAMES         ", portnum, (0x4603A218U));
    cpsw_print_stat_nonzero("RXJABBERFRAMES            ", portnum, (0x4603A21CU));
    cpsw_print_stat_nonzero("RXUNDERSIZEDFRAMES        ", portnum, (0x4603A220U));
    cpsw_print_stat_nonzero("RXFRAGMENTS               ", portnum, (0x4603A224U));
    cpsw_print_stat_nonzero("ALE_DROP                  ", portnum, (0x4603A228U));
    cpsw_print_stat_nonzero("ALE_OVERRUN_DROP          ", portnum, (0x4603A22CU));
    cpsw_print_stat_nonzero("RXOCTETS                  ", portnum, (0x4603A230U));
    cpsw_print_stat_nonzero("TXGOODFRAMES              ", portnum, (0x4603A234U));
    cpsw_print_stat_nonzero("TXBROADCASTFRAMES         ", portnum, (0x4603A238U));
    cpsw_print_stat_nonzero("TXMULTICASTFRAMES         ", portnum, (0x4603A23CU));
    cpsw_print_stat_nonzero("TXPAUSEFRAMES             ", portnum, (0x4603A240U));
    cpsw_print_stat_nonzero("TXDEFERREDFRAMES          ", portnum, (0x4603A244U));
    cpsw_print_stat_nonzero("TXCOLLISIONFRAMES         ", portnum, (0x4603A248U));
    cpsw_print_stat_nonzero("TXSINGLECOLLFRAMES        ", portnum, (0x4603A24CU));
    cpsw_print_stat_nonzero("TXMULTCOLLFRAMES          ", portnum, (0x4603A250U));
    cpsw_print_stat_nonzero("TXEXCESSIVECOLLISIONS     ", portnum, (0x4603A254U));
    cpsw_print_stat_nonzero("TXLATECOLLISIONS          ", portnum, (0x4603A258U));
    cpsw_print_stat_nonzero("RXIPGERROR                ", portnum, (0x4603A25CU));
    cpsw_print_stat_nonzero("TXCARRIERSENSEERRORS      ", portnum, (0x4603A260U));
    cpsw_print_stat_nonzero("TXOCTETS                  ", portnum, (0x4603A264U));
    cpsw_print_stat_nonzero("OCTETFRAMES64             ", portnum, (0x4603A268U));
    cpsw_print_stat_nonzero("OCTETFRAMES65T127         ", portnum, (0x4603A26CU));
    cpsw_print_stat_nonzero("OCTETFRAMES128T255        ", portnum, (0x4603A270U));
    cpsw_print_stat_nonzero("OCTETFRAMES256T511        ", portnum, (0x4603A274U));
    cpsw_print_stat_nonzero("OCTETFRAMES512T1023       ", portnum, (0x4603A278U));
    cpsw_print_stat_nonzero("OCTETFRAMES1024TUP        ", portnum, (0x4603A27CU));
    cpsw_print_stat_nonzero("NETOCTETS                 ", portnum, (0x4603A280U));
    cpsw_print_stat_nonzero("RX_BOTTOM_OF_FIFO_DROP    ", portnum, (0x4603A284U));
    cpsw_print_stat_nonzero("PORTMASK_DROP             ", portnum, (0x4603A288U));
    cpsw_print_stat_nonzero("RX_TOP_OF_FIFO_DROP       ", portnum, (0x4603A28CU));
    cpsw_print_stat_nonzero("ALE_RATE_LIMIT_DROP       ", portnum, (0x4603A290U));
    cpsw_print_stat_nonzero("ALE_VID_INGRESS_DROP      ", portnum, (0x4603A294U));
    cpsw_print_stat_nonzero("ALE_DA_EQ_SA_DROP         ", portnum, (0x4603A298U));
    cpsw_print_stat_nonzero("ALE_BLOCK_DROP            ", portnum, (0x4603A29CU));
    cpsw_print_stat_nonzero("ALE_SECURE_DROP           ", portnum, (0x4603A2A0U));
    cpsw_print_stat_nonzero("ALE_AUTH_DROP             ", portnum, (0x4603A2A4U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI              ", portnum, (0x4603A2A8U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI_BCNT         ", portnum, (0x4603A2ACU));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT              ", portnum, (0x4603A2B0U));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT_BCNT         ", portnum, (0x4603A2B4U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD              ", portnum, (0x4603A2B8U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD_BCNT         ", portnum, (0x4603A2BCU));
    cpsw_print_stat_nonzero("ALE_POL_MATCH             ", portnum, (0x4603A2C0U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_RED         ", portnum, (0x4603A2C4U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_YELLOW      ", portnum, (0x4603A2C8U));
    cpsw_print_stat_nonzero("TX_MEMORY_PROTECT_ERROR   ", portnum, (0x4603A37CU));

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x4603A380U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_REG             ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x4603A3A0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_BCNT_REG        ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x4603A3C0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_REG        ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x4603A3E0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_BCNT_REG   ", portnum, i, regAddr);
    }
}

void cpsw_ng_statsprint_nonzero(uint32_t numMacPorts)
{
    uint32_t i, regAddr, portnum;
    uint32_t baseAddr;
    printf("          STATS          \n");

    portnum = 0;
    printf("--------------------------------\n");
    printf("          PORT%d STATS          \n",portnum);
    printf("--------------------------------\n");
    cpsw_print_stat_nonzero("RXGOODFRAMES              ", portnum, (0x0C03A000U));
    cpsw_print_stat_nonzero("RXBROADCASTFRAMES         ", portnum, (0x0C03A004U));
    cpsw_print_stat_nonzero("RXMULTICASTFRAMES         ", portnum, (0x0C03A008U));
    cpsw_print_stat_nonzero("RXCRCERRORS               ", portnum, (0x0C03A010U));
    cpsw_print_stat_nonzero("RXOVERSIZEDFRAMES         ", portnum, (0x0C03A018U));
    cpsw_print_stat_nonzero("RXUNDERSIZEDFRAMES        ", portnum, (0x0C03A020U));
    cpsw_print_stat_nonzero("RXFRAGMENTS               ", portnum, (0x0C03A024U));
    cpsw_print_stat_nonzero("ALE_DROP                  ", portnum, (0x0C03A028U));
    cpsw_print_stat_nonzero("ALE_OVERRUN_DROP          ", portnum, (0x0C03A02CU));
    cpsw_print_stat_nonzero("RXOCTETS                  ", portnum, (0x0C03A030U));
    cpsw_print_stat_nonzero("TXGOODFRAMES              ", portnum, (0x0C03A034U));
    cpsw_print_stat_nonzero("TXBROADCASTFRAMES         ", portnum, (0x0C03A038U));
    cpsw_print_stat_nonzero("TXMULTICASTFRAMES         ", portnum, (0x0C03A03CU));
    cpsw_print_stat_nonzero("TXOCTETS                  ", portnum, (0x0C03A064U));
    cpsw_print_stat_nonzero("OCTETFRAMES64             ", portnum, (0x0C03A068U));
    cpsw_print_stat_nonzero("OCTETFRAMES65T127         ", portnum, (0x0C03A06CU));
    cpsw_print_stat_nonzero("OCTETFRAMES128T255        ", portnum, (0x0C03A070U));
    cpsw_print_stat_nonzero("OCTETFRAMES256T511        ", portnum, (0x0C03A074U));
    cpsw_print_stat_nonzero("OCTETFRAMES512T1023       ", portnum, (0x0C03A078U));
    cpsw_print_stat_nonzero("OCTETFRAMES1024TUP        ", portnum, (0x0C03A07CU));
    cpsw_print_stat_nonzero("NETOCTETS                 ", portnum, (0x0C03A080U));
    cpsw_print_stat_nonzero("RX_BOTTOM_OF_FIFO_DROP    ", portnum, (0x0C03A084U));
    cpsw_print_stat_nonzero("PORTMASK_DROP             ", portnum, (0x0C03A088U));
    cpsw_print_stat_nonzero("RX_TOP_OF_FIFO_DROP       ", portnum, (0x0C03A08CU));
    cpsw_print_stat_nonzero("ALE_RATE_LIMIT_DROP       ", portnum, (0x0C03A090U));
    cpsw_print_stat_nonzero("ALE_VID_INGRESS_DROP      ", portnum, (0x0C03A094U));
    cpsw_print_stat_nonzero("ALE_DA_EQ_SA_DROP         ", portnum, (0x0C03A098U));
    cpsw_print_stat_nonzero("ALE_BLOCK_DROP            ", portnum, (0x0C03A09CU));
    cpsw_print_stat_nonzero("ALE_SECURE_DROP           ", portnum, (0x0C03A0A0U));
    cpsw_print_stat_nonzero("ALE_AUTH_DROP             ", portnum, (0x0C03A0A4U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI              ", portnum, (0x0C03A0A8U));
    cpsw_print_stat_nonzero("ALE_UNKN_UNI_BCNT         ", portnum, (0x0C03A0ACU));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT              ", portnum, (0x0C03A0B0U));
    cpsw_print_stat_nonzero("ALE_UNKN_MLT_BCNT         ", portnum, (0x0C03A0B4U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD              ", portnum, (0x0C03A0B8U));
    cpsw_print_stat_nonzero("ALE_UNKN_BRD_BCNT         ", portnum, (0x0C03A0BCU));
    cpsw_print_stat_nonzero("ALE_POL_MATCH             ", portnum, (0x0C03A0C0U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_RED         ", portnum, (0x0C03A0C4U));
    cpsw_print_stat_nonzero("ALE_POL_MATCH_YELLOW      ", portnum, (0x0C03A0C8U));
    cpsw_print_stat_nonzero("TX_MEMORY_PROTECT_ERROR   ", portnum, (0x0C03A17CU));

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x0C03A180U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_REG             ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x0C03A1A0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_BCNT_REG        ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x0C03A1C0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_REG        ", portnum, i, regAddr);
    }

    for (i = 0; i < 8; i++)
    {
        regAddr = 0x0C03A1E0U + (i * 0x4U);
        cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_BCNT_REG   ", portnum, i, regAddr);
    }

    for (portnum = 1; portnum <= numMacPorts; portnum++)
    {
        printf("--------------------------------\n");
        printf("          PORT%d STATS          \n",portnum);
        printf("--------------------------------\n");
        baseAddr = 0x0C03A200U + ((portnum-1) * 0x200);

        cpsw_print_stat_nonzero("RXGOODFRAMES              ", portnum, (baseAddr));
        cpsw_print_stat_nonzero("RXBROADCASTFRAMES         ", portnum, (baseAddr + 0x4U));
        cpsw_print_stat_nonzero("RXMULTICASTFRAMES         ", portnum, (baseAddr + 0x8U));
        cpsw_print_stat_nonzero("RXPAUSEFRAMES             ", portnum, (baseAddr + 0xCU));
        cpsw_print_stat_nonzero("RXCRCERRORS               ", portnum, (baseAddr + 0x10U));
        cpsw_print_stat_nonzero("RXALIGNCODEERRORS         ", portnum, (baseAddr + 0x14U));
        cpsw_print_stat_nonzero("RXOVERSIZEDFRAMES         ", portnum, (baseAddr + 0x18U));
        cpsw_print_stat_nonzero("RXJABBERFRAMES            ", portnum, (baseAddr + 0x1CU));
        cpsw_print_stat_nonzero("RXUNDERSIZEDFRAMES        ", portnum, (baseAddr + 0x20U));
        cpsw_print_stat_nonzero("RXFRAGMENTS               ", portnum, (baseAddr + 0x24U));
        cpsw_print_stat_nonzero("ALE_DROP                  ", portnum, (baseAddr + 0x28U));
        cpsw_print_stat_nonzero("ALE_OVERRUN_DROP          ", portnum, (baseAddr + 0x2CU));
        cpsw_print_stat_nonzero("RXOCTETS                  ", portnum, (baseAddr + 0x30U));
        cpsw_print_stat_nonzero("TXGOODFRAMES              ", portnum, (baseAddr + 0x34U));
        cpsw_print_stat_nonzero("TXBROADCASTFRAMES         ", portnum, (baseAddr + 0x38U));
        cpsw_print_stat_nonzero("TXMULTICASTFRAMES         ", portnum, (baseAddr + 0x3CU));
        cpsw_print_stat_nonzero("TXPAUSEFRAMES             ", portnum, (baseAddr + 0x40U));
        cpsw_print_stat_nonzero("TXDEFERREDFRAMES          ", portnum, (baseAddr + 0x44U));
        cpsw_print_stat_nonzero("TXCOLLISIONFRAMES         ", portnum, (baseAddr + 0x48U));
        cpsw_print_stat_nonzero("TXSINGLECOLLFRAMES        ", portnum, (baseAddr + 0x4CU));
        cpsw_print_stat_nonzero("TXMULTCOLLFRAMES          ", portnum, (baseAddr + 0x50U));
        cpsw_print_stat_nonzero("TXEXCESSIVECOLLISIONS     ", portnum, (baseAddr + 0x54U));
        cpsw_print_stat_nonzero("TXLATECOLLISIONS          ", portnum, (baseAddr + 0x58U));
        cpsw_print_stat_nonzero("RXIPGERROR                ", portnum, (baseAddr + 0x5CU));
        cpsw_print_stat_nonzero("TXCARRIERSENSEERRORS      ", portnum, (baseAddr + 0x60U));
        cpsw_print_stat_nonzero("TXOCTETS                  ", portnum, (baseAddr + 0x64U));
        cpsw_print_stat_nonzero("OCTETFRAMES64             ", portnum, (baseAddr + 0x68U));
        cpsw_print_stat_nonzero("OCTETFRAMES65T127         ", portnum, (baseAddr + 0x6CU));
        cpsw_print_stat_nonzero("OCTETFRAMES128T255        ", portnum, (baseAddr + 0x70U));
        cpsw_print_stat_nonzero("OCTETFRAMES256T511        ", portnum, (baseAddr + 0x74U));
        cpsw_print_stat_nonzero("OCTETFRAMES512T1023       ", portnum, (baseAddr + 0x78U));
        cpsw_print_stat_nonzero("OCTETFRAMES1024TUP        ", portnum, (baseAddr + 0x7CU));
        cpsw_print_stat_nonzero("NETOCTETS                 ", portnum, (baseAddr + 0x80U));
        cpsw_print_stat_nonzero("RX_BOTTOM_OF_FIFO_DROP    ", portnum, (baseAddr + 0x84U));
        cpsw_print_stat_nonzero("PORTMASK_DROP             ", portnum, (baseAddr + 0x88U));
        cpsw_print_stat_nonzero("RX_TOP_OF_FIFO_DROP       ", portnum, (baseAddr + 0x8CU));
        cpsw_print_stat_nonzero("ALE_RATE_LIMIT_DROP       ", portnum, (baseAddr + 0x90U));
        cpsw_print_stat_nonzero("ALE_VID_INGRESS_DROP      ", portnum, (baseAddr + 0x94U));
        cpsw_print_stat_nonzero("ALE_DA_EQ_SA_DROP         ", portnum, (baseAddr + 0x98U));
        cpsw_print_stat_nonzero("ALE_BLOCK_DROP            ", portnum, (baseAddr + 0x9CU));
        cpsw_print_stat_nonzero("ALE_SECURE_DROP           ", portnum, (baseAddr + 0xA0U));
        cpsw_print_stat_nonzero("ALE_AUTH_DROP             ", portnum, (baseAddr + 0xA4U));
        cpsw_print_stat_nonzero("ALE_UNKN_UNI              ", portnum, (baseAddr + 0xA8U));
        cpsw_print_stat_nonzero("ALE_UNKN_UNI_BCNT         ", portnum, (baseAddr + 0xACU));
        cpsw_print_stat_nonzero("ALE_UNKN_MLT              ", portnum, (baseAddr + 0xB0U));
        cpsw_print_stat_nonzero("ALE_UNKN_MLT_BCNT         ", portnum, (baseAddr + 0xB4U));
        cpsw_print_stat_nonzero("ALE_UNKN_BRD              ", portnum, (baseAddr + 0xB8U));
        cpsw_print_stat_nonzero("ALE_UNKN_BRD_BCNT         ", portnum, (baseAddr + 0xBCU));
        cpsw_print_stat_nonzero("ALE_POL_MATCH             ", portnum, (baseAddr + 0xC0U));
        cpsw_print_stat_nonzero("ALE_POL_MATCH_RED         ", portnum, (baseAddr + 0xC4U));
        cpsw_print_stat_nonzero("ALE_POL_MATCH_YELLOW      ", portnum, (baseAddr + 0xC8U));
        cpsw_print_stat_nonzero("TX_MEMORY_PROTECT_ERROR   ", portnum, (baseAddr + 0x17CU));

        for (i = 0; i < 8; i++)
        {
            regAddr = (baseAddr + 0x180U) + (i * 0x4U);
            cpsw_print_stat_with_index_nonzero("TX_PRI_REG             ", portnum, i, regAddr);
        }

        for (i = 0; i < 8; i++)
        {
            regAddr = (baseAddr + 0x1A0U) + (i * 0x4U);
            cpsw_print_stat_with_index_nonzero("TX_PRI_BCNT_REG        ", portnum, i, regAddr);
        }

        for (i = 0; i < 8; i++)
        {
            regAddr = (baseAddr + 0x1C0U) + (i * 0x4U);
            cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_REG        ", portnum, i, regAddr);
        }

        for (i = 0; i < 8; i++)
        {
            regAddr = (baseAddr + 0x1E0U) + (i * 0x4U);
            cpsw_print_stat_with_index_nonzero("TX_PRI_DROP_BCNT_REG   ", portnum, i, regAddr);
        }
    }
}

void cpsw_5g_statsprint_nonzero()
{
    cpsw_ng_statsprint_nonzero(CPSW_5G_PORT_NUM);
}

void cpsw_9g_statsprint_nonzero()
{
    cpsw_ng_statsprint_nonzero(CPSW_9G_PORT_NUM);
}

void cpsw_clear_stat(uint32_t regAddr)
{
    uint32_t regVal = mmio_read_32(regAddr);
    mmio_write_32(regAddr, regVal);
}

void cpsw_2g_clear_stats()
{
    uint32_t portnum, baseAddr, numStats;

    for (portnum = 0; portnum <= CPSW_2G_PORT_NUM; portnum++)
    {
        baseAddr = 0x4603A000U + (portnum * 0x200);

        printf("Clearing stats for port[%d]\n", portnum);
        for (numStats = 0; numStats < 128U; numStats++)
        {
            cpsw_clear_stat(baseAddr + (numStats*0x4));
        }
    }

    printf("--------CLEARED ALL STATS-------\n");
}

void show_ale_entry_multicast_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - Multicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_MASK        = %x\n", (word2 >>  2) & 0x1FF);
    printf("SUPER            = %u\n", (word2 >>  1) & 0x1);
    printf("MCAST_FWD_STATE  = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("MULTICAST_ADDR   = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_multicast_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - Multicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_MASK        = %x\n", (word2 >>  2) & 0x1FF);
    printf("SUPER            = %u\n", (word2 >>  1) & 0x1);
    printf("MCAST IGNORE BITS= %u\n", (word2 >>  0) & 0x1);
    printf("MCAST_FWD_STATE  = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("MULTICAST_ADDR   = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_vlan_multicast_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN/Multicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_MASK        = %x\n", (word2 >>  2) & 0x1FF);
    printf("SUPER            = %u\n", (word2 >>  1) & 0x1);
    printf("MCAST_FWD_STATE  = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("VLAN_ID          = %u\n", (word1 >> 16) & 0xFFF);
    printf("MULTICAST_ADDR   = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_vlan_multicast_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN/Multicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_MASK        = %x\n", (word2 >>  2) & 0x1FF);
    printf("SUPER            = %u\n", (word2 >>  1) & 0x1);
    printf("MCAST_FWD_STATE  = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("VLAN_ID          = %u\n", (word1 >> 16) & 0xFFF);
    printf("MULTICAST_ADDR   = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_unicast_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_NUMBER      = %u\n", (word2 >>  2) & 0x1FF);
    printf("BLOCK            = %u\n", (word2 >>  1) & 0x1);
    printf("SECURE           = %u\n", (word2 >>  0) & 0x1);
    printf("UNICAST_TYPE     = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("UNICAST_ADDR     = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_unicast_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("TRUNK            = %u\n", (word2 >> 10) & 0x1);
    printf("PORT_NUMBER      = %u\n", (word2 >> 2) & 0xF);
    printf("BLOCK            = %u\n", (word2 >> 1) & 0x1);
    printf("SECURE           = %u\n", (word2 >> 0) & 0x1);
    printf("TOUCH            = %u\n", (word1 >> 31) & 0x1);
    printf("AGEABLE          = %u\n", (word1 >> 30) & 0x1);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("UNICAST_ADDR     = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_oui_unicast_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - OUI Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("UNICAST_TYPE     = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("UNICAST_OUI      = %x %x\n", (word1 >>  0) & 0xFFFF, (word0 >> 24) & 0xFF);
}

void show_ale_entry_oui_unicast_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - OUI Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("ENTRY_TYPE       = %u\n", (word1 >> 28) & 0x3);
    printf("UNICAST_OUI      = %x %x\n", (word1 >>  0) & 0xFFFF, (word0 >> 24) & 0xFF);
}

void show_ale_entry_vlan_unicast_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN/Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("PORT_NUMBER       = %u\n", (word2 >>  2) & 0x1FF);
    printf("BLOCK             = %u\n", (word2 >>  1) & 0x1);
    printf("SECURE            = %u\n", (word2 >>  0) & 0x1);
    printf("UNICAST_TYPE      = %u\n", (word1 >> 30) & 0x3);
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("VLAN_ID           = %u\n", (word1 >> 16) & 0xFFF);
    printf("UNICAST_ADDR      = %x %x\n", (word1 >>  0) & 0xFFFF, word0);
}

void show_ale_entry_vlan_unicast_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN/Unicast\n", index);
    printf("---------------------------------------------\n");
    printf("TRUNK             = %u\n", (word2 >> 10) & 0x1);
    printf("PORT_NUMBER       = %u\n", (word2 >> 2) & 0x1FF);
    printf("BLOCK             = %u\n", (word2 >> 1) & 0x1);
    printf("TOUCH             = %u\n", (word1 >> 31) & 0x1);
    printf("AGEABLE           = %u\n", (word1 >> 30) & 0x1);
    printf("SECURE            = %u\n", (word2 >> 0) & 0x1);
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("VLAN_ID           = %u\n", (word1 >> 16) & 0xFFF);
    printf("UNICAST_ADDR      = %x %x\n", (word1 >> 0) & 0xFFFF, word0);
}

void show_ale_entry_vlan_2g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN\n", index);
    printf("---------------------------------------------\n");
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("VLAN_ID           = %u\n", (word1 >> 16) & 0xFFF);
    printf("FORCE_UNTAG_EG    = %u\n", (word0 >> 24) & 0x1FF);
    printf("REG_MCAST_FLOOD   = %u\n", (word0 >> 16) & 0x1FF);
    printf("UNREG_MCAST_FLOOD = %u\n", (word0 >>  8) & 0x1FF);
    printf("VLAN_MEMBER_LIST  = %u\n", (word0 >>  0) & 0x1FF);
}

void show_ale_entry_vlan_inner_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN INNER \n", index);
    printf("---------------------------------------------\n");
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("IVLAN_ID           = %u\n", (word1 >> 16) & 0xFFF);
    printf("NO FRAG           = %u\n", (word1 >> 15) & 0x1);
    printf("REG_MCAST_FLOOD   = %u\n", (word1 >> 4) & 0x1FF);
    printf("VLAN FWD Untagged Egress = %u\n",
                                ((word1 >> 0U) & 0x100) + (word0 >> 24) & 0x1FF);
    printf("LMT NEXT HDR      = %u\n", (word0 >> 23) & 0x1);
    printf("UNREG_MCAST_FLOOD = %u\n", (word0 >> 12) & 0x1FF);
    printf("VLAN_MEMBER_LIST  = %u\n", (word0 >>  0) & 0x1FF);
}

void show_ale_entry_vlan_outer_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN OUTER\n", index);
    printf("---------------------------------------------\n");
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("OVLAN_ID           = %u\n", (word1 >> 16) & 0xFFF);
    printf("NO FRAG           = %u\n", (word1 >> 15) & 0x1);
    printf("REG_MCAST_FLOOD   = %u\n", (word1 >> 4) & 0x1FF);
    printf("VLAN FWD Untagged Egress = %u\n",
                                ((word1 >> 0U) & 0x100) + (word0 >> 24) & 0x1FF);
    printf("LMT NEXT HDR      = %u\n", (word0 >> 23) & 0x1);
    printf("UNREG_MCAST_FLOOD = %u\n", (word0 >> 12) & 0x1FF);
    printf("VLAN_MEMBER_LIST  = %u\n", (word0 >>  0) & 0x1FF);
}

void show_ale_entry_vlan_ethertype_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN ETHERTYPE \n", index);
    printf("---------------------------------------------\n");
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("ETHERTYPE  = %u\n", (word0 >>  0) & 0xFFFF);
}

void show_ale_entry_vlan_ip4_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN IPV4 \n", index);
    printf("---------------------------------------------\n");
    printf("IGNORE BITS       = %u\n", (word2 >> 1) & 0x1F);
    printf("ENTRY_TYPE        = %u\n", (word1 >> 28) & 0x3);
    printf("IPV4 ADDR  = %u\n", word0);
}

void show_ale_entry_vlan_ip6_9g(uint32_t index, uint32_t word0, uint32_t word1, uint32_t word2)
{
    printf("---------------------------------------------\n");
    printf(" Entry %u - VLAN IPV6 \n", index);
    printf("---------------------------------------------\n");
    printf("Understanding Gap hence not printing :(");
}

void cpsw_print_ale_table_2g()
{
    uint32_t word0, word1, word2;
    uint32_t type;
    int i;

    printf("---------------------------------------------\n");
    printf("-------CPSW2G ALE TABLE----------------------\n");
    printf("---------------------------------------------\n");

    for (i = 0; i < ALE_TABLE_DEPTH_2G; i++)
    {
        mmio_write_32(ALE_TBLCTL_2G, i);

        word0 = mmio_read_32(ALE_TBLW0_2G);
        word1 = mmio_read_32(ALE_TBLW1_2G);
        word2 = mmio_read_32(ALE_TBLW2_2G);

        if (0)
        {

            printf("WORD1  = %u\n", word0);
            printf("WORD1  = %u\n", word1);
            printf("WORD1  = %u\n", word2);
        }

        /* ENTRY_TYPE (bits 61:60) */
        type = (word1 >> 28) & 0x3;

        if (type == ALE_ENTRY_EMTPY) {
            //printf(" Entry %u - Empty\n", i);
        } else if (type == ALE_ENTRY_ADDR) {
            if ((word1 >> 8) & 0x1) {
                show_ale_entry_multicast_2g(i, word0, word1, word2);
//            } else if ((word1 >> 30) & 0x3) {
//                show_ale_entry_oui_unicast(i, word0, word1, word2);
            } else {
                show_ale_entry_unicast_2g(i, word0, word1, word2);
            }
        } else if (type == ALE_ENTRY_VLAN) {
            show_ale_entry_vlan_2g(i, word0, word1, word2);
        } else if (type == ALE_ENTRY_VLAN_ADDR) {
            if ((word1 >> 8) & 0x1) {
                show_ale_entry_vlan_multicast_2g(i, word0, word1, word2);
            } else {
                show_ale_entry_vlan_unicast_2g(i, word0, word1, word2);
            }
        }
    }

    printf("Completed analysis of %u ALE entries\n", i);
}

void cpsw_print_ale_table_ng(int numAleEntries)
{
    uint32_t word0, word1, word2;
    uint32_t type;
    uint32_t vlanEntryType;
    int i;

    printf("---------------------------------------------\n");
    printf("-------CPSWnG ALE TABLE----------------------\n");
    printf("---------------------------------------------\n");
    for (i = 0; i < numAleEntries; i++)
    {
        mmio_write_32(ALE_TBLCTL_9G, i);

        word0 = mmio_read_32(ALE_TBLW0_9G);
        word1 = mmio_read_32(ALE_TBLW1_9G);
        word2 = mmio_read_32(ALE_TBLW2_9G);

        if (0)
        {
            printf("WORD0  = %x\n", word0);
            printf("WORD1  = %x\n", word1);
            printf("WORD2  = %x\n", word2);
        }

        /* ENTRY_TYPE (bits 61:60) */
        type = (word1 >> 28) & 0x3;

        if (type == ALE_ENTRY_EMTPY)
        {
            //printf(" Entry %u - Empty\n", i);
        }
        else if (type == ALE_ENTRY_ADDR)
        {
            if ((word1 >> 8) & 0x1)
            {
                show_ale_entry_multicast_9g(i, word0, word1, word2);
            }
            else if ( ((word1 >> 30) & 0x3) == 0x2 )
            {
               show_ale_entry_oui_unicast_9g(i, word0, word1, word2);
            }
            else
            {
                show_ale_entry_unicast_9g(i, word0, word1, word2);
            }
        }
        else if (type == ALE_ENTRY_VLAN)
        {
            vlanEntryType = ((word1 >> 30) & 0x3);
            vlanEntryType |= ((word2 >> 0) & 0x1);

            if ( 0x0 == vlanEntryType)
            {
                show_ale_entry_vlan_inner_9g(i, word0, word1, word2);
            }
            else if ( 0x2 == vlanEntryType)
            {
                show_ale_entry_vlan_outer_9g(i, word0, word1, word2);
            }
            else if ( 0x4 == vlanEntryType)
            {
                show_ale_entry_vlan_ethertype_9g(i, word0, word1, word2);
            }
            else if ( 0x6 == vlanEntryType )
            {
                show_ale_entry_vlan_ip4_9g(i, word0, word1, word2);
            }
            else if ((word1 >> 30) & 0x1)
            {
                show_ale_entry_vlan_ip6_9g(i, word0, word1, word2);
            }

        }
        else if (type == ALE_ENTRY_VLAN_ADDR)
        {
            if ((word1 >> 8) & 0x1)
            {
                show_ale_entry_vlan_multicast_9g(i, word0, word1, word2);
            }
            else {
                show_ale_entry_vlan_unicast_9g(i, word0, word1, word2);
            }
        }
    }

    printf("Completed analysis of %u ALE entries\n", i);
}

void cpsw_print_ale_table_5g()
{
    cpsw_print_ale_table_ng(ALE_TABLE_DEPTH_5G);
}

void cpsw_print_ale_table_9g()
{
    cpsw_print_ale_table_ng(ALE_TABLE_DEPTH_9G);
}

void cpsw_ng_clear_stats(uint32_t numMacPorts)
{
    uint32_t portnum, baseAddr, numStats;

    for (portnum = 0; portnum <= numMacPorts; portnum++)
    {
        baseAddr = 0x0C03A000U + (portnum * 0x200);

        printf("Clearing stats for port[%d]\n",portnum);
        for (numStats = 0; numStats < 128U; numStats++)
        {
            cpsw_clear_stat(baseAddr + (numStats*0x4));
        }
    }

    printf("--------CLEARED ALL STATS-------\n");
}

void cpsw_5g_clear_stats()
{
    cpsw_ng_clear_stats(CPSW_5G_PORT_NUM);
}

void cpsw_9g_clear_stats()
{
    cpsw_ng_clear_stats(CPSW_9G_PORT_NUM);
}

int main()
{
    int input;
    while(1)
    {
        printf("===============================\n");
        printf("\t     Menu\n");
        printf("===============================\n");
        
        printf("0: Clear Stats : CPSW 2G\n");
        printf("1: Clear Stats : CPSW 5G\n");
        printf("2: Clear Stats : CPSW 9G\n");
        printf("3: Print Stats : CPSW 2G\n");
        printf("4: Print Stats : CPSW 5G\n");
        printf("5: Print Stats : CPSW 9G\n");
        printf("6: Print ALE : CPSW 2G\n");
        printf("7: Print ALE : CPSW 5G\n");
        printf("8: Print ALE : CPSW 9G\n");
        printf("9: Print Enet CFG : CPSW 2G\n");
        printf("10: Print Enet CFG : CPSW 5G\n");
        printf("11: Print Enet CFG : CPSW 9G\n");
        printf("12: Verify Enet Ctrl CFG : CPSW 2G\n");
        printf("13: Verify Enet Ctrl CFG : CPSW 5G\n");
        printf("14: Verify Enet Ctrl CFG : CPSW 9G\n");
        printf("15: Print MAC Config : CPSW 2G\n");
        printf("16: Print MAC Config : CPSW 5G\n");
        printf("17: Print MAC Config : CPSW 9G\n");
        printf("18: Print 5G RGMII regs\n");

        printf("Make your choice : ");
        scanf("%d", &input);

        switch(input)
        {
            case 0:
            cpsw_2g_clear_stats();
            break;

            case 1:
            cpsw_5g_clear_stats();
            break;

            case 2:
            cpsw_9g_clear_stats();
            break;

            case 3:
            cpsw_2g_statsprint_nonzero();
            break;

            case 4:
            cpsw_5g_statsprint_nonzero();
            break;

            case 5:
            cpsw_9g_statsprint_nonzero();
            break;

            case 6:
            cpsw_print_ale_table_2g();
            break;

            case 7:
            cpsw_print_ale_table_5g();
            break;

            case 8:
            cpsw_print_ale_table_9g();
            break;

            case 9:
            Cpsw2g_PrintEnetCtrl();
            break;

            case 10:
            Cpsw5g_PrintEnetCtrl();
            break;

            case 11:
            Cpsw9g_PrintEnetCtrl();
            break;

            case 12:
            Board_Cpsw2g_VerifyEnetCtrl();
            break;

            case 13:
            Board_Cpsw5g_VerifyEnetCtrl();
            break;

            case 14:
            Board_Cpsw9g_VerifyEnetCtrl();
            break;

            case 15:
            Cpsw2g_PrintMACCfg();
            break;

            case 16:
            Cpsw5g_PrintMACCfg();
            break;

            case 17:
            Cpsw9g_PrintMACCfg();
            break;

            case 18:
            Cpsw5g_printKeyMiiRegs();
            break;

            default:
            printf("Unknown option\n");
            break;

        }
        
    }
    
}

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet，

    Thanks for your reply,  the statistic of cpsw macport 5 is below

    as the result, tx frame is good, but it can not be received by phy, as the rgmii tx_clk is in wrong frequency(2.5Mhz), and I have check the rgmii5 status, it is in 10M speed mode, rgmii 6 is in 100M speed mode. it should be noted that, rgmii 5 and 6 are in the same configuration in my code 

    with regards

  • 0 in reply to jeffreysundts
    Intellectual 460 points

    Hi Vineet，

    We also found that rgmii5 is always in mac tx idle, but for other rgmii is not in the idle state, Is that effect the rgmii tx clk and how to solve it?

    with regards 

  • 0 in reply to jeffreysundts
    Intellectual 460 points

    We also found that rgmii5_tx_ctl rx_ctl tx_d and rx_d is with no signal; rgmii rx_clk is 25Mhz; data can be received by phy from PC to TDA4 board

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    This is a gentle reminder, please reply to the query.

  • 0 in reply to jeffreysundts
    TI__Expert 3585 points

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/906169/tda4vm-tda4vm-ethernet-switch-cpsw-9g-configurations 

    I'm finding a summary about the changes should be taken care for CPSW9 mac configuration. Not sure if you ever saw this but please revisit to see if anything were missing. 

    In meanwhile, Vineet will work on high priority to provide further update and fix. 

  • 0 in reply to Xu(SH) Liu
    TI__Mastermind 37435 points

    Hi Jeffrey,

    Apologies for the delay.

    I will try to resolve your problem at the earliest

    Can you print out the RGMII config at your end by using option 19

    8032.cpsw_all_reg_print.c

    I am attaching my output as a reference, look at Port 4 which has link-up

    CTRLMMR_ENET1_CTRL : 0x12
    CTRLMMR_ENET2_CTRL : 0x4
    CTRLMMR_ENET3_CTRL : 0x12
    CTRLMMR_ENET4_CTRL : 0x12
    CTRLMMR_ENET5_CTRL : 0x6
    CTRLMMR_ENET6_CTRL : 0x6
    CTRLMMR_ENET7_CTRL : 0x6
    CTRLMMR_ENET8_CTRL : 0x12
    CTRLMMR_CPSW_CLKSEL : 0x0
    RGMII1_STATUS : 0x3
    RGMII2_STATUS : 0x0
    RGMII3_STATUS : 0x3
    RGMII4_STATUS : 0xd
    RGMII5_STATUS : 0x0
    RGMII6_STATUS : 0x0
    RGMII7_STATUS : 0x0
    RGMII8_STATUS : 0x3
    MAC_CONTROL_1 : 0x20000
    MAC_CONTROL_2 : 0x0
    MAC_CONTROL_3 : 0x20000
    MAC_CONTROL_4 : 0x200a1
    MAC_CONTROL_5 : 0x0
    MAC_CONTROL_6 : 0x0
    MAC_CONTROL_7 : 0x0
    MAC_CONTROL_8 : 0x20000

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    Thanks for your reply,  mac port 5 is linked up and the value of registers is attached ：

    CTRLMMR_ENET5_CTRL : 0x12

    RGMII5_STATUS : 0x0

    MAC_CONTROL_5 : 0x20000

    With regards

  • 0 in reply to jeffreysundts
    TI__Mastermind 37435 points

    Hi Jeffrey,

    MAC is reporting that link is not up. Let me see what else we can check

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    TI__Mastermind 37435 points
    jeffreysundts said:
    Thanks for your reply,  mac port 5 is linked up and the value of registers is attached

    Why do you mention that link is up ? Is it based on PHY LED ?

    In your earlier logs I found these two lines

    [MCU2_0]   4608.797581 s: EnetPhy_findCommonNwayCaps: PHY 2: no common caps found
    [MCU2_0]   4608.797688 s: Cpsw_handleLinkUp: Port 6: Link up: 1-Gbps Full-Duplex

    It doesn't say that Port 5 link is up

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    Mac port5 is configured in 100M mode as shown below

    Thanks

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    We have applied the same configuration for mac port 5 and 6, and mac port 6 works properly both for 100M and 1G mode

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    We have applied three macport(6,2,5), only macport 5 is not working 

    I'd also like to clear up three points:

    1. PHY3 is connected with macport 5; as shown in the log attached before : macport 5 is linked up but I think that means the phy connected with mac is linked up;

    2.RGMII5_STATUS : 0x0, I think that the value of rgmii indicates the status of macport is not linked 

    3. rgmii5_txclk is 2.5Mhz, the case is same with the rgmii4 which is not connected with phy, and when we connected the rgmii4 with phy, the frequency is changed to 25Mhz (100M speed mode).

    4.We can not detected the rgmii_tx data from mac

    So I want to ask for your advices about what could be the reason for phy linked up but mac is not linked .

    Thanks

  • 0 in reply to jeffreysundts
    Intellectual 460 points

    Hi Vineet,

    The pinumux setting of rgmii5 is attached , and the read-back value is same as setiing

        /*rxd0*/

        *((uint32_t volatile *)(0x0011C184)) =0x00050000;
        /*rxd1*/
        *((uint32_t volatile *)(0x0011C180)) =0x08214000;
        /*rxd2*/
        *((uint32_t volatile *)(0x0011C17C)) =0x08214000;
        /*rxd3*/
        *((uint32_t volatile *)(0x0011C178)) =0x08214000;
        /*rxctl*/
        *((uint32_t volatile *)(0x0011C15C)) =0x00000000;
        /*rxclk*/
        *((uint32_t volatile *)(0x0011C174)) =0x00000000;
        /*txd0*/
        *((uint32_t volatile *)(0x0011C16C)) =0x08214000;
        /*txd1*/
        *((uint32_t volatile *)(0x0011C168)) =0x08214000;
        /*txd2*/
        *((uint32_t volatile *)(0x0011C164)) =0x00000000;
        /*txd3*/
        *((uint32_t volatile *)(0x0011C160)) =0x00000000;
        /*txctl*/
        *((uint32_t volatile *)(0x0011C158)) =0x00000000;
        /*txclk*/
     
  • 0 in reply to jeffreysundts
    TI__Mastermind 37435 points

    Hi Jeffrey,

    Can we try a small experiment ?

    Can you force write bit 5 (GMII_EN) to 1 in CPSW_PN_MAC_CONTROL_REG_k register for Port 5

    Please also provide the Option 19 dump (with script shared earlier) for working ports ?

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    I try to force write GMII_EN to 1, the bit is always 1

    and for CTRLMMR_ENET1_CTRL register, the value of macport 5 and working ports are same, which are 0x12

    with regards

  • 0 in reply to jeffreysundts
    TI__Mastermind 37435 points

    Hi Jeffrey,

    jeffreysundts said:
    I try to force write GMII_EN to 1, the bit is always 1

    I see, but earlier when you reported the values from script, the value was 0.

    jeffreysundts said:

    CTRLMMR_ENET5_CTRL : 0x12

    RGMII5_STATUS : 0x0

    MAC_CONTROL_5 : 0x20000

    Any idea what changed ? Did the value change upon writing to it ?

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    TI__Expert 3585 points

    Vineet, can you check if the pinmux customer provided 1 day ago are all correct?

  • 0 in reply to Vineet Roy
    Intellectual 460 points

    Hi Vineet,

    • We have changed the pinumux of rgmii5 to following values, then the rgmii5 works

    these value have benn changed, and I wonder what these value used for? Do these configured registers have no effects on other modules?

    Thanks

  • 0 in reply to jeffreysundts
    TI__Expert 3585 points

    Bit 18 maybe the key point to this issue.