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AM3359: Challenge faced in configuring GPMC using DTS file

Rishabh Mishra
Prodigy 50 points
Part Number: AM3359
Other Parts Discussed in Thread: SYSCONFIG

Dear TI Support Team,

We are trying to configure the GPMC in AM3359 processor using DTS, our GPMC is communicating with end device(ARTIX 7 FPGA) on Chip Select "3".

I am referring to the Documentation provided with the Linux source code.

Path: Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

Still we are facing challenge with configuring GPMC_SYSCONFIG, GPMC_IRQENABLE, GPMC_STATUS and CONFIG 7 using DTS.

can you please provide some information as how or which field we can configure in DTS.

We have attached our required GPMC registers value and read back value below.

-----expected-----
mwr 0x50000010 0x00000008
mwr 0x5000001C 0x00000200
mwr 0x50000054 0x00000000
mwr 0x50000108 0x00000f50

----Received-----
root@RCU:~# mrd 0x50000010 0x1
0x00000011
root@RCU:~# mrd 0x5000001C 0x1
0x00000000
root@RCU:~# mrd 0x50000054 0x1
0x00000301
root@RCU:~# mrd 0x50000108 0x1
0x00000F43

Also, we have attached the DTS node for GPMC below

&gpmc {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mygpmc1_pins_default>;
    #address-cells = <2>;
    #size-cells = <1>;

    ranges = < 0 0 0x08000000 0x01000000    /*CD0: 256MB for NAND 0x1000000 */
                         3 0 0x03000000 0x01000000>;  /*CS3: configuration memory
                                                                                    mapping 127KB for FPGA GPMC */

    r4_gpmc: r4_gpmc@50000000 {
        compatible = "ti,omap-gpmc";
        reg = <3 0 0x01000000>;  /* CS3, offset 0, IO size 4*/
        interrupt-parent = <&gpmc>;
        interrupt-controller;
        interrupts = <2 IRQ_TYPE_EDGE_FALLING>, /* GPMC Wait0 active low*/
                             <3 IRQ_TYPE_EDGE_FALLING>; /* GPMC Wait1 active low*/
        #interrupts-cells = <2>;
        gpmc,num-cs = <6>;
        gpmc,num-waitpins = <2>;
        gpmc,sync-clk-ps = <10000>;
        /*GPMC Config 2 details*/
        gpmc,cs-on-ns = <0>;
        gpmc,cs-rd-off-ns = <290>;
        gpmc,cs-wr-off-ns = <90>;
        /*GPMC Config 3 details*/
        gpmc,adv-on-ns = <0>;
        gpmc,adv-rd-off-ns = <10>;
        gpmc,adv-wr-off-ns = <10>;
        gpmc,we-on-ns = <20>;
        gpmc,we-off-ns = <80>;
        gpmc,adv-aad-mux-on-ns = <0>;
        gpmc,adv-aad-mux-rd-off-ns = <0>;
        gpmc,adv-aad-mux-wr-off-ns = <0>;
        /*GPMC Config 4 details*/
        gpmc,oe-on-ns = <30>;
        gpmc,oe-off-ns = <290>;
        gpmc,oe-aad-mux-on-ns = <0>;
         /*GPMC Config 5,6 wait-monitoring-ns details*/
        gpmc,page-burst-access-ns = <10>;
        gpmc,access-ns = <80>;
        gpmc,rd-cycle-ns = <310>;
        gpmc,wr-cycle-ns = <310>;
        gpmc,bus-turnaround-ns = <0>;
        gpmc,cycle2cycle-delay-ns = <20>;
        gpmc,clk-activation-ns = <10>;
        gpmc,wait-monitoring-ns = <10>;
        /*GPMC Boolean timing parameters*/
        gpmc,cycle2cycle-diffcsen = "true";
        gpmc,cycle2cycle-samecsen = "true";
        /*GPMC OMAP3+ & AM335x parameters*/
        gpmc,wr-access-ns = <20>;
        gpmc,wr-data-mux-bus-ns = <30>;
        /*GPMC chip select settings*/
        gpmc,burst-read = <0>;
        gpmc,burst-write = <0>;
        gpmc,burst-wrap = <0>;
        gpmc,device-width = <2>; /*1 for 8 & 2 for 16 bit*/
        gpmc,mux-add-data = <2>;
        gpmc,sync-read = <1>;
        gpmc,sync-write = <1>;
        gpmc,wait-pin = <1>;
        gpmc,wait-on-read = <1>;
        gpmc,wait-on-write = <1>;
        gpmc,device-nand = "false";
    };
};

Best Regards,

Rishabh Mishra

  • 0
    TI__Guru*** 125756 points

    Hi Rishabh,

    Did you review the kernel driver drivers/memory/omap-gpmc.c? It shows how the DTS values are translated to GPMC register settings.

  • 0 in reply to Bin Liu
    Prodigy 50 points

    Hi Bin Liu,

    Thanks for the quick response.
    Yes I reviewed the kernel driver at drivers/memory/omap-gpmc.c.

    I tried applying the calculations and found that to get 0x450 as register value I need to set ranges value for GPMC as <3 0 0x10000000 0x01000000> but this results in an error at zImage while booting.

    Here is the error message received.
    omap-gpmc 50000000.gpmc: GPMC revision 6.0
    gpmc_mem_init: disabling cs 3 mapped at 0x10000000-0x11000000
    omap-gpmc 50000000.gpmc: cannot remap GPMC CS 3 to 0x10000000
    omap-gpmc 50000000.gpmc: failed to probe DT child 'r4_gpmc': -16

    For the other registers like GPMC_SYSCONFIG, GPMC_IRQENABLE, GPMC_STATUS I found the control to be at "omap3_gpmc_restore_context" but this is not getting invoked.

    Can you explain or provide me with a value that i can use to get 0x450 and set the other registers.

    Thanks and Regards,
    Rishabh Mishra

  • 0 in reply to Rishabh Mishra
    Prodigy 50 points

    Hi Bin Liu,

    We were able to perform reads and writes using 0x03000000 base address with <3 0 0x03000000 0x01000000>
    ranges values and other GPMC_SYSCONFIG, GPMC_IRQENABLE, GPMC_STATUS configuration values.

    I was wondering why we were not able to set 0x10000000 as the base address for GPMC.

    Can you help us understand this better?
    Thanks again for the reply earlier.

    Thanks and Regards,
    Rishabh Mishra

  • 0 in reply to Rishabh Mishra
    TI__Guru*** 125756 points

    Hi Rishabh,

    Rishabh Mishra said:
    I was wondering why we were not able to set 0x10000000 as the base address for GPMC.

    Do you still see the kernel remap error log with error code -16? I am not sure what causes it. Please review your kernel device tree file to see if the address range has been used elsewhere. If not, can you please debug the kernel gpmc driver init routine to understand why it fails with -16 error?