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Original question:

AM3359: GPMC Read transaction issue with AD mode configuration

AM3359: GPMC ALE and ADDR alignment was inconsistent!

ti_user
Expert 1265 points
Part Number: AM3359

Dear Experts,

The custom board design housed with an AM3359 processor connected with an FPGA over GPMC interface, which is operating at 100MHz, Synchronous & Multiplexed mode.

The AM3359 processor is running with Linux SDK v6.1.

There is an issue with address placement on the bus and ALE alignment is inconsistent. Attached the snapshots for understanding and highlighted with clock mismatch output.

The alignment of ALE and ADDR is proper in some transactions, image as follows,

Please share your inputs and possible reasons behind this.

Thanks

  • 0
    TI__Mastermind 29290 points

    Hi,

    Can you please provide register values (see list below) for whichever chip select you are using? Have you measured the CLK, ADVn, and couple signals from AD bus with an oscilloscope to see if the timings are marginal?

    You may be able to get more margin by adjusting CLKACTIVATIONTIME, ADVEXTRADELAY parameters of GPMC registers.

    GPMC_CONFIG1_n
    GPMC_CONFIG2_n
    GPMC_CONFIG3_n
    GPMC_CONFIG4_n
    GPMC_CONFIG5_n
    GPMC_CONFIG6_n
    GPMC_CONFIG7_n

    Regards,
    Mark

  • 0 in reply to Mark Mckeown
    Expert 1265 points

    Hi Mark,

    The GPMC configurations used in dts are as follows,

     /* CONFIG1 */
            bank-width = <2>;           /* GPMC_CONFIG1_DEVICESIZE(1) */
            gpmc,burst-read;
            gpmc,burst-write;
            /*gpmc,burst-wrap;*/
            gpmc,sync-read;             /* GPMC_CONFIG1_READTYPE_ASYNC */
            gpmc,sync-write;            /* GPMC_CONFIG1_WRITETYPE_ASYNC */
            gpmc,clk-activation-ns = <10>;       /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
            gpmc,burst-length = <16>;       /* GPMC_CONFIG1_PAGE_LEN(2) */
            gpmc,mux-add-data = <2>;        /* GPMC_CONFIG1_MUXTYPE(2) */

            /*GPMC Config 2 details*/
            /* CONFIG2 */
            gpmc,sync-clk-ps = <10000>; /* Mininum clock period for synchronous mode, in picoseconds */
            gpmc,cs-on-ns = <10>;
            gpmc,cs-wr-off-ns = <40>;
            gpmc,cs-rd-off-ns = <210>;

            /*C4*/
            gpmc,oe-off-ns = <210>;

            /*C5*/
            gpmc,access-ns = <170>;
            gpmc,rd-cycle-ns = <210>;

            /*GPMC Config 3 details*/
            /* CONFIG3 */
            gpmc,adv-on-ns = <10>;
            gpmc,adv-rd-off-ns = <30>;
            gpmc,adv-wr-off-ns = <30>;

            /*GPMC Config 4 details*/
            /* CONFIG4 */
            gpmc,we-on-ns = <30>;
            gpmc,we-off-ns = <40>;
            gpmc,oe-on-ns = <30>;

            /* CONFIG 5 */
            gpmc,page-burst-access-ns = <10>;
            gpmc,wr-cycle-ns = <50>;

            /* CONFIG 6 */
            gpmc,wr-access-ns = <40>;
            gpmc,wr-data-mux-bus-ns = <30>;
            gpmc,bus-turnaround-ns = <50>;
            gpmc,cycle2cycle-samecsen;
            gpmc,cycle2cycle-delay-ns = <40>;

    We measured the clock its 100MHz.

    Thanks