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DRA821U: Intermediate potential before internal Pull enabling

Part Number: DRA821U

Hi

Is the internal Pullup/Pulldown enabled in SBL (Secondary Boot Loader)?

Is there an intermediate potential and through current between device power-up and internal pullup/pulldown enabled (until SBL processing is complete)?

Does this damage the device?

What is the resistance of the internal pullup/Pulldown?

Thanks and Best regards,

Tsurumoto.

  • The default state of the internal PU or PD is defined in the data manual, and is enabled by the ROM (prior to SBL).  It is possible the SBL adjust the default configuration (software teams can confirm).  There is not an intermediate state with both PU and PD is enabled (at power up), and it would not damage the device.   

    The resistance value is 15K to 30K-ohms for both PU and PD 

  • Hi

    I got additional question about it.


    1)

    After SBL, if Hi-Z input pins or Hi-Z bidirectional pins are an intermediate potential and through current

    then it damages the device?


    2)
    About the pins which "BALL RESET STATE" is "OFF" or "blank", those are intermediate potential and through current between power up and enabling PU/PD at SBL .
    Does it damage the device?
    User need put external PU/PD for the pins?

    3)
    If the internal PU/PD resistor value is 15k~30k, can the resistor value be less than 4.7k Ω to be logically fixed with the external PU/PD?
    The supply current of the PU/PD is approximately 0.4 mA per terminal at 1.8 V supply.
    In total, it's going to be a few tens to 100mA. It's a big figure, so let me check it out just in case.
  • 1)  It is recommended to avoid 'floating' inputs as it is possible pins can be damaged.  Pins should not be held at intermediate state.

    2) No - should be OK enabling PU/PD at SBL.

    3) Yes, pull value can be less than 4.7kOhms.  If setting as output (to over-drive PU/PD), just make sure IO max current is not exceeded.