AM4378: Intermediate potential

This is a valid concern. Applying a mid-supply potential to any CMOS input buffer that is enabled will partially turn on both p-channel and n-channels in the input buffer. This causes shoot-through current to flow from the IO supply to ground. This shoot-through current could damage the input buffer if the condition remains for extended periods of time. Therefore, it is important for the system design to turn off any conflicting internal pulls as soon as possible.

Based on the register values provided in the table above, ROM code appears to be turning off the internal pulls before it begins the boot process. So this concern is already being addressed by the eMMC boot ROM code. This could be a problem if a eMMC device is connected as described above and the eMMC boot ROM code never executes. Your system software would need to take care of this if you select a different boot mode and the ROM code never turns off the pull-downs.

Regards,
Paul

Hi Paul,

Thank you for your reply.
I will share it with my customer.

Best regards,
Kanae

Why are you asking the same question on two separate threads?

I would recommend adding external pulls in addition to the conflicting internal pulls, where the external pull impedance is able to pull the signal to a valid logic level until one or both internal pulls can be turned off. This will minimize the risk if the system encounters an unexpected event that prevents it from booting and the intermediate level is applied for a longer period than expected.

Regards,
Paul  

I'm not sure if I understand the use case they are asking about.

Are they asking if it is okay to leave the conflict which applies a mid-supply potential when the signal is not driven by one of the attached devices? For example, a bidirectional data signal that is driven most of the time but occasionally not driven by either device when there is a data direction change.

If so, this is not recommended. This use case could cause long-term reliability issues for the input buffer since the accumulated time spent in the undesired mid-supply region could add up to a significant amount of time over the rated POH of the device.

If their use case is different than my description above, please provide more details.

They should limit total accumulated exposure time to this condition.

Regards,
Paul

Shoot-through current will look like a narrow bell-shaped curve when plotted on the y-axis with respect to input voltage on the x-axis, where the current peaks as the input voltage reaches approximately VDD/2. The primary goal needed to reduce long-term reliability risk associated with an intermediate voltage is reducing shoot-through current by getting the input voltage as close as possible to VSS or the respective VDDSHVx power rails.

The JEDEC eMMC standard only defines internal pulls for DAT[7:1] pins and requires the eMMC deice to turn off these internal pulls once it is configured to transfer data on these pins. So eMMC internal resistors should be off when the device is being used and the system software should have already turned off the internal conflicting pull-down resistors in AM437x. So there should be no concern with intermediate voltage during normal operation. 

I agree, the signal will have three pulls connected before software is initialized. There is no concern from the JEDEC eMMC standard perspective with this combination of pulls being outside of the 10k to 150K range until communication begins. So you should be able to use a 10K external pull on these signals since the internal pulls will be turned off before communications begins. This will pull the input as high as possible without violating the JEDEC eMMC standard pull-up requirement.  I'm not sure what the input voltage will be while all three resistors are enabled, but hopefully the external 10K pull-up is able to pull the voltage high enough above the VDD/2 potential that shoot-through current is significantly reduced.

Q1. Is there any problem to pull down the external pull-up resistor with a lower value
than that specified by JEDEC?

A1. I'm not sure if I understand this question. Are you asking if the IO can source enough current to pull-down a stronger pull-up? If so, you would need to check the VOL/IOL parameters of the device driving the signal and the VIL requirements of the device receiving the signal to know how much current a IO can sink while still providing a valid input to the other device. 

Q2. When connecting an eMMC to MMC1 of AM437x, does this mean
that a resistor of 10kΩ or less (e.g. 1kΩ) is recommended?

A2. I do not recommend violating the pull requirements defined in an industry standard.

Q3. if you want to avoid deviating from the pull-up resistor range specified by JEDEC,
"minimize the risk of encountering an unexpected situation where the system cannot boot
and intermediate levels are applied for a longer period than expected"
Since it is stated that "the intermediate potential is acceptable for a limited time during the reset period",
is this acceptable?　If so, please let me know the time.

A3. As mentioned in A2, I do not recommend violating the pull requirements defined in an industry standard.  We have not define a time limit for an intermediate voltage condition. The customer needs to do the best they can to minimize the time the device is exposed to this condition and get the intermediate voltage as close as possible to VSS or the respective VDDSHVx power rails.

If the customer doesn't feel comfortable with the risk associated with an intermediate voltage condition, they may need to insert an isolation circuit between the two devices. However, this type of circuit could insert significant delays in the signal paths and cause timing problems for the peripheral. The AM437x device has been in production for several years. There are many similar designs and we have not received any reports related to this concern.

Regards,
Paul

Hi Paul,

Thank you for your support.

I will share it with my customer.

Best regards,
Kanae