Hi,
As shown in the screenshot, the DSP core can be reset by generating a local reset by the watchdog. Can I reset a certain DSP core through the watchdog (Timer16) of the arm core when SOC running? If it is possible, how to configure it?
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Hi,
As shown in the screenshot, the DSP core can be reset by generating a local reset by the watchdog. Can I reset a certain DSP core through the watchdog (Timer16) of the arm core when SOC running? If it is possible, how to configure it?
Hi Nancy,
As per 66AK2H12 datasheet, In "10.2.3.19 Reset Mux (RSTMUXx) Register", OMODE defines the reset for which core to happen.
When OMODE=010b, for DSP CorePac, the WD timer output is routed to the local reset input of the CorePac LPSC through RSTMUX block.
For ARM, as there is no local reset for ARM possible, the WD timer output of ARM watchdog is routed to device reset.
When OMODE=101b, the WD timer output is routed to device reset for both DSP CorePac and ARM core.
Also refer this Post for further clarification, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/253812/watchdog-implementation-66ak2h12
Thanks,
Rajarajan U