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TDA4VM：Questions about UDMAP module register access restrictions.

Yuan Stone
Prodigy 40 points
Part Number: TDA4VM

Hi all,

      I'm reading the chip manual for TDA4VM (SPRUIL1B.pdf) and have some doubts about the content of the description of the UDMAP register:

        Taking the UDMASS_UDMAP0_CFG_TCHANRT register as an example, the description in the manual is as follows:

         

        But in the chip manual I didn't find a description about the cdma_cfg_resl signal.

        I noticed the description was due to my attempt to read the register, which resulted in a kernel panic.

        My question is what should I do ahead of time in the code if I want to access this register?

Looking forward to your reply。

Best Regards

  • 0
    Prodigy 40 points

    Oh~

    Who can help me? 

    I'm trying to adapt an OS to tda4vm, but I can't access the real time register of UDMA module.

    I looked up some information (e.g, https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_01_00_13/exports/docs/pdk_jacinto_08_01_00_36/docs/pdk_introduction.html#Documentation), which mentioned the need to configure the sending or receiving channel firewall (implemented through tisci) before accessing the real time register.

    In fact, I sent instructions in the format on this page, but I still can't access it.

    I don't know what the crux of the problem is. 

    Look forward to your help!

    3ks

  • 0 in reply to Yuan Stone
    TI__Guru** 100221 points

    Hi,

    Regarding "adapt an OS to tda4vm, but I can't access the real time register of UDMA module".

    Not sure if this will help with what you're after but the UDMA from the PSDK RTOS release has been ported to run on QNX.  In the case of the TI SDK QNX, UDMA implementation,  memory mapping to the physical addresses were required in order to get virtual addresses.  Searching on the QNX_OS build flag, in the psdkqa/pdk/packages/ti/drv/udma directory in any of the PSDK QNX packages, you can see the changes made for the QNX port.

    Regarding the picture above, the APIs for the "Channel Config" are shown in the copy of this same slide at UDMA Overview.    The Udma_chConfigTx(chHandle, &txPrms), results in a call to Sciclient_rmUdmapTxChCfg(), which in turn sends an SCI message to the DMSC/SMS for processing.  See TISCI UserGuide J721E DMA Device Descriptions — TISCI User Guide, and Resource Management UDMAP TISCI Message Description — TISCI User Guide.

    Regards,

    kb

  • 0 in reply to KB
    Prodigy 40 points

    Hi KB,
    Thank you for your reply, I will check my code following the demo in PSDK.
    I want to confirm the following two questions:

    1. Does the operation of 'Core-A72' requesting the DMSC for 'channel configuration' permissions depend on other preconditions?
      1. I sent a 'TISCI_MSG_RM_UDMAP_TX_CH_CFG' type packet according to the TISCI protocol and checked the ACK, but the exception still occurred when accessing the 'UDMA RCHANRT' register.
      2. In order to confirm the status of the DMSC, before sending the 'TISCI_MSG_RM_UDMAP_TX_CH_CFG', I sent the 'TISCI_MSG_VERSION' message packet to the DMSC, and the version number can be successfully obtained.
    2. Is there any debugging method to check if DMSC successfully sets up the ‘firewall’?
      1. Maybe I should try the method in 'Firewall FAQ', don't know if there are other means.

    Regards,

    Stone

  • 0 in reply to KB
    Prodigy 40 points

    Hi KB,

    After a few days of fumbling around, I found out that the reason for not being able to access the registers was that my driver was running at EL0.

    Depending on the configuration in u-boot, I tried to access the corresponding register (UDMASS_UDMAP0_CFG_TCHANRT) at the EL1 privilege level through the system call interface, and successfully obtained the data in the register.

    Is the above phenomenon a hardware limitation of TDA4VM?

    3ks~~~

    Stone