This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] 66AK2E05: TSIP on K2E DSP

Part Number: 66AK2E05

How to run TSIP project from TI-RTOS SDK on DSP core of K2E processor?

  • To run the TSIP (T1 / E1) Example project for K2E devices make sure the pre-requisites are done.

    1. Install CCS (Version : 9.03) installed (,
    2. Install PROCESSOR-SDK-RTOS-K2E (Version : 06_03_00_106) (,
    3. Generate PDK examples (

    Now Import the CCS project into CCS and go on

    1. To Import the project goto File -> Import -> "CCS projects" in "C/C++" -> Browse "Select Search-directory". make sure to uncheck the "Copy Projects into Workspace" (This is to avoid compilation errors only If TI-RTOS SDK was installed in a different location than "C:\ti\").
    2. Now, we have the DSP example project ("TSIP_K2E_C66ExampleProject") and currently "TSIP_K2E_C66TestProject" will run only with proper TSIP connections. (Do not open ARM and DSP examples at the same time, CCS will throw project out-of-sync error dialog).
      1. Without external TSIP connections, the Example project will configure and Open the TSIP port, But the data transfer will not be completed.
      2. For various TSIP configurations, Code modifications need to be done in "Sample.c".
        void tsipConfig (tsipSizeInfo_t *sizeCfg, tsipConfig_t *cfg)
            /* Provide size information for TSIP */
            sizeCfg->maxChannels = TSIP_MAX_TIMESLOTS;
            sizeCfg->subFrameSize = 8;
            sizeCfg->wordSize = 8;
        	sizeCfg->validParams = TSIP_SIZE_INFO_VALIDPARAMS_NUM_PORTS;
        	sizeCfg->numPorts = NUM_USED_TSIP_PORTS;
            /* Global configuration */
            cfg->testMode = TRUE;
            cfg->testModeSelect = CSL_TSIP_TESTMODE_DATA_LOOPBACK;
            cfg->clkRedund = CSL_TSIP_CLKD_REDUN;
            cfg->endian = CSL_TSIP_ENDIAN_LITTLE;
            cfg->priority = CSL_TSIP_PRI_0;
            cfg->maxPriority = CSL_TSIP_PRI_0;
            cfg->sizeCfg = sizeCfg;
            cfg->maxPhase = 10;
            /* Transmit configuration */
            cfg-> = deviceWhoAmI();
            cfg->tx.frameSize = CSL_TSIP_FRAMESIZE_128;
            cfg->tx.tsPerFrame = 256;
            cfg->tx.clkSrc = CSL_TSIP_CLKSRC_A;
            cfg->tx.dataDelay = 1;
            cfg->tx.bdxDelay = CSL_TSIP_DLY_CTRL_DISABLE;
            cfg->tx.idleDrive = CSL_TSIP_XMTDIS_HIGHIMP;
            cfg->tx.fsyncPol = CSL_TSIP_FSYNCP_ALOW;
            cfg->tx.fsyncClkPol = CSL_TSIP_CLKP_RISING;
            cfg->tx.clkPol = CSL_TSIP_CLKP_RISING;
            cfg->tx.dataRate = CSL_TSIP_DATARATE_16M;
            cfg->tx.clkMode = CSL_TSIP_CLKM_SGL;
            cfg->tx.superFrameInt = CSL_TSIP_INT_ACK;
            cfg->tx.frameInt = CSL_TSIP_INT_ACK;
            cfg->tx.frameIntDelay = 0;
            /* Receive configuration */
            cfg-> = deviceWhoAmI();
            cfg->rx.frameSize = CSL_TSIP_FRAMESIZE_128; 
            cfg->rx.tsPerFrame = 256;
            cfg->rx.clkSrc = CSL_TSIP_CLKSRC_A;
            cfg->rx.dataDelay = 1;
            cfg->rx.bdxDelay = CSL_TSIP_DLY_CTRL_DISABLE;
            cfg->rx.fsyncPol = CSL_TSIP_FSYNCP_ALOW;
            cfg->rx.fsyncClkPol = CSL_TSIP_CLKP_RISING;
            cfg->rx.clkPol = CSL_TSIP_CLKP_FALLING;
            cfg->rx.dataRate = CSL_TSIP_DATARATE_16M;
            cfg->rx.clkMode = CSL_TSIP_CLKM_SGL;
            cfg->rx.superFrameInt = CSL_TSIP_INT_ACK;
            cfg->rx.frameInt = CSL_TSIP_INT_ACK;
            cfg->rx.frameIntDelay = 0;
      3. Documentation on TSIP CSL API functions and Macro definitions are present in following loation is SDK "{K2E_PDK_INSTALLATION_FOLDER}/packages/ti/drv/tsip/docs/doxygen/html/index.html" (Open this file chrome browser for better viewing).
      4. K2E Project Log, we can only verify API functionality and Port status in the processor from this log. After connecting the TSIP hardware, we can confirm the Full duplex communication.
        [C66xx_0] **************************************************
        ******* TSIP Example Start ***********************
        TSIP port 0 is powered up
        TSIP driver instance successfully initialized 
        TSIP port instance successfully initialized 
        TSIP port 0 super frame interrupt is registered
        Initialize application buffers before TSIP-APP transfer
        Enabling TSIP timeslot TX 0 RX 0... 
        TSIP timeslot TX 0 RX 0 successfully enabled 
        TSIP data transfer...
      5. SDK documentation Link:
      6. For TSIP connections in EVM, refer to this document K2E_EVM_SCH_16_00175_03.pdf

    Thanks & Regards,

    Rajarajan U