Hi team,
Here's an issue from the customer may need your help:
When Master and Slave are communicating full duplex (dual TDA4 MCU communicating MCSPI0), data overlay on slave side Rx data and Tx data (verify master side Tx data is OK with logic analyzer; Tx data on slave side is abnormal. And the read Rx data is also abnormal).
The exception data frame will have 32byte error data with the contents of the data sent from the previous frame and the location of the 32byte error data is random. It is possible to be in the middle of or between the header and end of the packet (a frame of data of 160byte length, using SetupEB and enabling DMA transfer mode). The probability of error occurring is approximately 10%, and the SPI communication cycle is 10 ms.
For example:
DATA1： 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATA2： 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DATA3： 3 3 3 3 3 3 2 2 2 2 2 3 3 3 3 3 3 （Random in the head, tail, or middle of the packet, Length is 32byte)
DATA4： 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Could you help check this case? Thanks.
Best Regards,
Cherry
