Other Parts Discussed in Thread: OMAPL138
Dear all, I can't find for this CPU a uart.h like this programming model :
struct UART_REGS_STRUCT
{
Uint32 RBR_THR; //Receiver Buffer Register (read only), Transmitter Holding Register (write only)
Uint32 IER; //Interrupt Enable Register
Uint32 IIR_FCR; //Interrupt Identification Register (read only), FIFO Control Register (write only)
Uint32 LCR; //Line Control Register
Uint32 MCR; //Modem Control Register
Uint32 LSR; //Line Status Register
Uint32 MSR; //Modem Status Register
Uint32 SCR; //Scratch Pad register
Uint32 DLL; //Divisor LSB Latch
Uint32 DLH; //Divisor MSB Latch
Uint32 REVID1; //Revision Identification Register 1
Uint32 REVID2; //Revision Identification Register 2
Uint32 PWREMU_MGMT; //Power and Emulation Management Register
Uint32 MDR; //Mode Definition Register
};
extern volatile struct UART_REGS_STRUCT UART0_REGS;
extern volatile struct UART_REGS_STRUCT UART1_REGS;
extern volatile struct UART_REGS_STRUCT UART2_REGS;
I wrote this by myself. Do you have a uart.h and an example withe the uart (FIFO, DMA included)?
Thanks
Martin