Hi team,
Working on developing a driver firmware which communicate with external slave device via SPI. According to the slave device data sheet it needs typical 3 micro second inter-byte (delay between each byte). SPI driver is sending data in FIFO mode and when we measure the delay,This is only 1.12 micro second for 1 Mhz SPI clock frequency.
Can we increase the inter-byte delay?. Is there any configuration register available to support this in FIFO or non-FIFO mode?
