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AM625: MMC2 Pinmuxing CLKB

Isee
Expert 6070 points
Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

On the AM62 SK DTS there is the following:

AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */

This is not present when generating the .dtsi using the sysconfig tool and it’s writing to a non documented registers.

Question was asked at another thread in the past with no answer - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1126003/am625-mmc2_clkb-in-k3-am625-sk-dts 

Do we need it to use the MMC2 interface as SDIO?

If yes:

  • what is this doing ?

  • where is this documented?

  • 0
    TI__Guru**** 155761 points

    Hi,

    I am working internally to understand this MMC2_CLKB pin and how it comes to the kernel DTS. I will get back to you once I have an update.

  • 0
    TI__Guru**** 155761 points

    Hi,

    I haven't received a response from our dev team yet, but I found the following note in the Datasheet. I believe this is the reason of this pinmux setting. The PADCONFIG71 register offset is 0x11c.

  • 0 in reply to Bin Liu
    TI__Expert 6070 points

    Do you have a feedback as yet?

    I agree, this is very likely this PADCONFIG71 mentioned on the datasheet section you pasted here.

    However if it must remains at default state why writing it?

    Moreover the value written in the TI DTS file is not the default, different bits are set. What is wrong? The datasheet or the DTS?

  • 0 in reply to Isee
    TI__Guru**** 155761 points

    Hi,

    Isee said:
    Do you have a feedback as yet?

    Not yet.

    Isee said:
    However if it must remains at default state why writing it?

    In many case, the kernel device tree still wants to specifically set the default state, to decouple any configuration state left from U-Boot.

    Isee said:
    Moreover the value written in the TI DTS file is not the default, different bits are set. What is wrong? The datasheet or the DTS?

    Yes, I noticed the Datasheet states the RXACTIVE bit default is 0x1, while the TRM register description section says RXACTIVE bit default is 0x0. I have filed a ticket to our documentation team to check this inconsistency.

  • 0 in reply to Bin Liu
    TI__Expert 6070 points

    REminder

  • 0 in reply to Isee
    TI__Expert 6070 points

    There is some pending action. Can you please follow up?

  • 0 in reply to Isee
    TI__Guru**** 155761 points

    The team is still working on clarifying the default value of the register and to update the documentation accordingly. But regardless, the RXACTIVE bit should be set to 1 as what the DTS pinmux does.

  • 0 in reply to Isee
    TI__Expert 6070 points

    Any update? please do not forget about this question about the inconsistency between mmc2 and mmc0/mmc1.

  • 0 in reply to Isee
    TI__Guru**** 155761 points

    Hi Isee,

    My apologies for missed updating this thread.

    The RXACTIVE bit in the PADCONFIG register for mmc0/mmc1 by default is 1, but it is default to 0 for mmc2. So the Linux device tree only sets it to 1 in mmc2 node, but not in mmc0/mmc1 nodes.