This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Correct, this is not fixed indeed. This is a System Integration aspect, and you can choose an appropriate value for your product. The address in TI SDK is just a reference example, and is the address arrived after reserving 16 MB for each core for firmware memory starting from 0xA0000000, and placing the IPC VRING memory at the end of the firmware memory sections. This does need to be matched across all.
The RTOS PDK IPC code is written with the base design that all required memory for IPC vring buffers are control structures are statically reserved. The SDK reserved 28 MB considering the possible superset use-case of treating MPU as a non-SMP core, and using 512 bytes for each vring buffer and 256 number of vring buffers in each direction, and assuming all cores are running RTOS or QNX.
The 28 MB (0x1C00000) is also a rounded figure to the nearest 1 MB boundary, but following is the computation used.
Number of Processors = 11 (6 R5Fs + 3 DSPs + 2 MPU A72 cores)
Number of buffers in each direction = 256
Size of each vring transport buffer (rpmsg header of 16 bytes + max payload of 496 bytes) = 512 bytes.
Total Size of vring buffers in one direction = 256 * 512 = 0x20000 bytes
The computation also reserved 0x20000 bytes for each vring structure leading to a total of 0x40000 bytes for vring buffers and vring structures.
There are a total of 11 processors, and two-way communications is needed between each pair of processors. The vrings and vring buffers are directional, so you will need 2 between a pair of processors, and so that is a classic N by (N-1) (11 * 10 in this case).
The overall size derived therefore was
11 * 10 * 0x40000 = 0x1B80000 ~ 0x1C00000.