I am using the AM4378 to drive a 800x480 TFT LCD. The Pixel Clock is set 30MHz. The unit is tested to CISPR 12, fails at 90MHz and 150MHz, and is failing around 10dB over the limit. I am 100% certain that the pixel clock is the issue. I have isolated by disconnecting all other LCD connections and disconnecting only the pixel clock. The issue is persistent in the former and goes away with the latter.
My questions:
- How does the processor generate the pixel clock?
- Is there a way to configure the edges / slew rate of the clock?
- Is there a way to reduce the drive strength of the clock?
- What knobs in general do I have to configure the clock?