AM4378: Pixel Clock cause of EMC failures

 Hello Brett Paulsen,

Thank you for the query.

With the above information, i am not sure how best i could support.

Do you have the series resistors on the PCLK and other control lines. Do you have all the recommended decaps and bulk caps on the processor.

Would you be Ok to share the schematics to have a quick look.

Regards,

Sreenivasa

Yes, I have 33ohm resistors on all of the control lines and the RGB data lines and processor is has all of the recommended capacitors.  Sharing the schematic would not be useful.  The LCD operates just fine.  

Can you answer my questions? 

 Hello Brett Paulsen,

Thank you for the note.

How does the processor generate the pixel clock?

Pls refer to below TRM section.

Chapter 13 

Display Subsystem (DSS)

13.6 Registers

13.6.1 DSS_DISPC Registers

DISPC_DIVISOR

I am checking on the availability of the capability for slew rate control or the drive strength control.

For clock related information please refer to TRM section as below 

Chapter 6 

Power, Reset, and Clock Management (PRCM)

Regards,

Sreenivasa

 Hello Brett Paulsen,

We do not recommend setting the slew rate since this configuration or setting has not been timing closed.

I received the below inputs from the device expert - Paul Eaves as below:

There is a good chance slowing the slew rate will impact signal timing margin and cause other issues.

 I suspect they are having problems because they are routing all of the parallel video output signals through a connector and cable to the display.  I think most customers that have encountered a similar issue found they need to include an on-board video serializer located near the processor, that uses low voltage signaling to send the video data off-board to the display.

 It is very difficult to route a high-bandwidth wide parallel bus across a cable from one PCB assembly to another without it radiating emissions.

 The only other solution that I’m aware of is designing their system with the appropriate shielding to prevent emissions from radiating.

Regards,

Sreenivasa

Hello Brett Paulsen,

Please refer below some additional inputs i received.

Response 1 

another idea for them is to enable spread spectrum on the display PLL which drives the pixel clock.  I’m not sure how well a display works with a jittery clock, but maybe this will help with peak energy at the frequencies they mention. 

Response 2 

In either case MPU or Display PLL, the customer should only configure the PLL to operate with down-spreading rather than symmetrical-spreading to prevent any increase in frequency generated by the spread from over-clocking any circuits in the clock path when operating near its max frequency limit.

Regards,

Sreenivasa

Hi Kallikuppa,

Thank you for the replies.  I was already pursuing shielding and LVDS options in parallel to these questions.  LVDS would be a good option, but the probability of changing the LCD at this point in the project is low.

The spread spectrum option is intriguing, and I will give it a try.  I agree that its success is dependent on the LCD operating correctly.  

Thanks,

Brett 

Hello Brett Paulsen,

Thank you for the inputs.

Can you also verify the recommended bulk caps and decaps for the processor are used.

In case you are using an oscillator, check if the supplies have the bulk caps.

Regards,

Sreenivasa