Hi Ti,
We are using several PRUs in AM65. And from TRM, there are IEP0 and IEP1 inside.
And if there any standard to choose IEP0 or IEP 1 for specific PRUs?
Thanks.
Eric
Can you paste IEP0 and IEP1 memory browser screenshots got the ICSSG instance used in non-working and working scenarios?
Not sure if this is what you want. Please let me know if I was wrong.
IEP1 (working)
IEP0 (non-working)
Eric
Looking at register dump, there is a problem with your IEP0 configuration, are you running this firmware stand alone or together with some Industrial Ethernet protocol ?
/* Set compare values*/IEPCounter.cmp0_reg0 = OutFreqMax_ns;IEPCounter.cmp0_reg1 = 0;
/* Enable CMP0 and reset on event */IEPCounter.cmp_cfg_reg_bit.cmp_en = 0x1; // enable CMP0 eventIEPCounter.cmp_cfg_reg_bit.cmp0_rst_cnt_en = 0x1; // enable the reset of counter
I do not see above taking effect for IEP0, but shadow_en bit set and IEPCounter.cmp0_reg0 = 0. So effectively your IEP count_reg0 will stay at zero always as seen from the logs! Can you try updating above registers via memory browser and see whether it works?
My PRU code is coming from our PRU engineer but the reason is unknown anymore.
After check with TRM, the shadow mode bit looks to enable 32 bit operation. Default is 64 bit.
And there is a sentence not very clear. Could you help to explain it?
"This enable the shadow copy finctionality of the compare registers"
Eric
I tired to do an experiment for my use case.
While I was running PRU0_1, I tried to control the R30 as high low.
__R30 = 0;
for(;;)
{
if (IEPCounter.cmp_status_reg_bit.cmp_status == 0x1) // CMP0 event is issued
{
/* Clear CMP0 status */
IEPCounter.cmp_status_reg_bit.cmp_status = 0x1;
break;
}
}
__R30 = 1;
Before control R30, we initialize the IEP1 timer below and got the waveform as below. It looks not bad.
/* Disable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0;
/* Reset Count register */
IEPCounter.count_reg0 = 0xFFFFFFFF;
IEPCounter.count_reg1 = 0xFFFFFFFF;
/* Clear overflow status register */
IEPCounter.global_status_reg_bit.cnt_ovf = 0x1;
/* Clear compare status */
IEPCounter.cmp_status_reg = 0xFFFFFFFF;
/* Set compare values*/
IEPCounter.cmp0_reg0 = OutFreqMax_ns;
IEPCounter.cmp0_reg1 = 0;
/* Enable CMP0 and reset on event */
IEPCounter.cmp_cfg_reg_bit.cmp_en = 0x1; // enable CMP0 event
IEPCounter.cmp_cfg_reg_bit.cmp0_rst_cnt_en = 0x1; // enable the reset of counter
/* Set increment value */
IEPCounter.global_cfg_reg_bit.default_inc = 4;
/* Disable compensation */
IEPCounter.compen_reg_bit.compen_cnt = 0x0;
/* Enable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0x1;
#pragma MUST_ITERATE(1)
for (i = 0; i < HSPO_Channel; i++, g_pSharedPoCrtl++)
{
g_pSharedPoCrtl->hspPOCr = HspPOTypeAB;
}
However, when I load PRU0_0, which is running with IEP0, and it only execute IEP setting here. The reset code are cyclic and I remove it for this test.
void IEPTimer_init(void)
{
#if defined(PRU0_0)
/* Set PRU Sync-to-VCLK Mode, Clock speed 250MHz*/
CT_CFG.core_sync_reg_bit.core_vbusp_sync_en = 1;
/* Set IEP as sync mode, the clock is 250MHz*/
CT_CFG.iepclk_reg_bit.iep_ocp_clk_en = 1;
#endif
/* Enable shadow mode*/
//IEPCounter.cmp_cfg_reg_bit.shadow_en = 1; //I already mark the shadow_en here.
/* Disable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0;
/* Reset Count register */
IEPCounter.count_reg0 = 0xFFFFFFFF;
IEPCounter.count_reg1 = 0xFFFFFFFF;
/* Set increment value */
IEPCounter.global_cfg_reg_bit.default_inc = 4;
/* Enable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0x1;
}
The R30 waveform controlled by PRU0_1 becomes not stable.
In my though, I don't think it's normal when running PRU0_0 and PRU0_1 at the same time.
so, could you help to how to do the IEP setting?
Thanks.
Eric
