This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6421: HSR (High-availability Seamless Redundancy) availability

Part Number: AM6421

Looking to begin working with the AM6421 running Linux

What is the status of HSR support from TI for HSR on PRUs? A TI employee mentioned they thought it would be included in SDK9.0 release in August but recommended I ask in this forum for confirmation.

Is it true that HSR is already supported for RTOS, but not for Linux yet?

  • Linux kernel based HSR is supported to day, wiht any two ethernet devices.

    Linux release plan for 1G HSR with switch offload is:

    Processor SDK 9.0

    Processor SDK 9.1

    Processor SDK 9.2

    14 Aug 2023

    30 NOV 2023

    15 MAR 2024

    HSR 1 G Switch offload (AM64)

    HSR 1G offload: TX tag insertion and packet duplication (AM64)

    HSR 1G offload: RX tag removal and packet duplicate discard (AM64)

    MCU+ RTOS has 100M HSR support today https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/HSR_PRP_FWHAL.html . We plan to migrate this to 1G and the same ICSSG firmware after Linux support.

      Pekka

  • Thanks, I am sorry but I do not fully understand your answer. Are you saying 100M HSR is available today as MPU+Linux, and the development schedule for 1G Linux is according to the chart you provided with 1G RTOS to follow?

    Where can my software team download (or find) the example code for 100M HSR on Linux today?

  • Are you saying 100M HSR is available today as MPU+Linux
    Where can my software team download (or find) the example code for 100M HSR on Linux today?

    Linux kernel based HSR is available today https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/HSR_PRP.html?highlight=hsr . This is using any Ethernet device on the SoC 100M or 1G, switching happens in the Ethernet driver. The table I shared is for switching offloaded. Or in other words https://www.kernel.org/doc/html/latest/networking/netdev-features.html hsr-fwd-offload feature is in SDK 9.0.

    On the R5 cores and MCU+ SDK 100M with switching offload the software is at https://www.ti.com/tool/download/MCU-PLUS-SDK-AM64X/08.06.00.43 .

  • Hello Pekka I appreciate the responses and clarifications. May I ask for one more?

    TI has example code for a 100M software-based HSR implementation in the driver (as I understood your answers) rather than a hardware implementation when using Linux. Hardware offloading will be supported by future releases of the SKD as mentioned above. I am not a software developer so forgive my need for simplification and clarity - based on the dates you provided it is not fully clear to me when we can consider the hardware offloaded solution available - is it not until March 2024? Is it not required that packet duplication and removal are necessary functions for an implementation of HSR?

    Also, the dates mention only 1G speed, will 100M be included in those dates through backwards compatibility?

  • the dates mention only 1G speed, will 100M be included in those dates through backwards compatibility?

    The AM64x ICSSG 1G HSR will also support 100M.

    TI has example code for a 100M software-based HSR implementation in the driver (as I understood your answers)

    This is actually in the mainline kernel starting at least in 5.4 , so any 2 Ethernet devices can be made to logically work as one HSR Ethernet device. This is independent of the interface speed, just dependent on SW performance to achieve switching of 1G of traffic.

    when we can consider the hardware offloaded solution available

    The HW offload can be viewed in steps. First and most critical is offloading the packet forwarding, or switching/bridging. If the Linux kernel does this in the driver, the bridge delay or per hop latency is going to be in dozen or so microseconds on average, with outliers in the hundreds of microseconds. And there will be a CPU load component for also switched traffic at every hop. This will go to zero CPU load, and a deterministic bridge delay of ~1us with the forwarding offload (HW cut-through, not store and forward).

    Tag insertion and duplicate drop are just minor CPU load savings at the source and destination processors.

    So with 9.0 SDK I would say HSR support is there. A further CPU performance increase at the source and endpoint (not the intermediate hops in the ring) is expected in the subsequent releases.