OMAPL138B-EP: Processors forum, EDMA dose not work with emulater XDS200

Hi 

 currently, I am debugging an old project with the OMAPL138ZWT with CCS7, and without RTOS. 

 EDMA  2x channel for the McBSP1 to read and write the ADC module. 

and the ADC value will finally be stored at one array ADCIN, and other functions can just use the data in ADCIN.

I checked there is only one function in the whole project as below for the DAC initialization and it is called once in the initialization stage when powered up. 

it works well in our existing board for years, but when I try to debug with Emulator XDS200, there is no reading from this array. 

it shows always 0, but I checked DRR 0x01D11000 in the memory, and there is data but non-zero.

It seems EDMA not working. 

Not sure why?  Thanks in advance. 

Flowing is our code.

_____________________

volatile unsigned int ADCIN[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
volatile unsigned int ADCOUT[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

void DmaInit(void)
{
/* DATA PARAMETERS PROVIDED BY APPLICATION */
// unsigned int chType = EDMA3_CHANNEL_TYPE_DMA;
unsigned int chNumR = EDMA3_CHA_MCBSP1_RX;
unsigned int tccNumR = EDMA3_CHA_MCBSP1_RX;
unsigned int chNumT = EDMA3_CHA_MCBSP1_TX;
unsigned int tccNumT = EDMA3_CHA_MCBSP1_TX;
//unsigned int edmaTC = EDMA3_TC_PI1;
unsigned int syncType = EDMA3_SYNC_A;
//unsigned int trigMode = EDMA3_TRIG_MODE_EVENT;
unsigned int evtQ = 0; /* Event Queue used */
unsigned int evtQ1 = 1; /* Event Queue used */
EDMA3CCPaRAMEntry paramSet, paramSet1;
unsigned int retVal, retVal1 = 0u;

unsigned short acnt = MAX_ACOUNT_ADCDATA;
unsigned short bcnt = MAX_BCOUNT_ADCDATA;
unsigned short ccnt = MAX_CCOUNT_ADCDATA;
/*
** Enable IRQ interrupt in DSP processor.
*/
// SetupINTCInt();

EDMA3Init(SOC_EDMA30CC_0_REGS, evtQ);
EDMA3Init(SOC_EDMA30CC_0_REGS, evtQ1);

// registerEdma3Interrupts();

/* ST1_ADDR->bitval.cpl = 0; *//* DP indirectly addressing */

/* ADC channels */

// ADCOUT[0] = 0x2008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/
// ADCOUT[1] = 0x2008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/
// ADCOUT[2] = 0x2008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/

// ADCOUT[3] = 0x2108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/
// ADCOUT[4] = 0x2108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/
// ADCOUT[5] = 0x2108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/

ADCOUT[0] = 0x0008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/
ADCOUT[1] = 0x0008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/
ADCOUT[2] = 0x0008; /*0000 0000 0000 1000; CH0, AVdd =3.3V*/

ADCOUT[3] = 0x0108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/
ADCOUT[4] = 0x0108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/
ADCOUT[5] = 0x0108; /*0000 0001 0000 1000: CH2, AVdd = 3.3V*/

ADCOUT[6] = 0x0208; /*0000 0010 0000 1000: CH4, AVdd = 3.3V*/
ADCOUT[7] = 0x0208; /*0000 0010 0000 1000: CH4, AVdd = 3.3V*/
ADCOUT[8] = 0x0208; /*0000 0010 0000 1000: CH4, AVdd = 3.3V*/

ADCOUT[9] = 0x0308; /*0000 0011 0000 1000: CH6, AVdd = 3.3V*/
ADCOUT[10] = 0x0308; /*0000 0011 0000 1000: CH6, AVdd = 3.3V*/
ADCOUT[11] = 0x0308; /*0000 0011 0000 1000: CH6, AVdd = 3.3V*/

/* Request DMA channel and TCC */
retVal1 = EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
chNumT, tccNumR, evtQ1);

/* Channel 5 to MCBSP Transmitter */
if (TRUE == retVal1)
{
/* Fill the PaRAM Set with transfer specific information */
paramSet1.srcAddr = (unsigned int)&ADCOUT;
paramSet1.destAddr = (unsigned int)DXR;

paramSet1.aCnt = (unsigned short)acnt;
paramSet1.bCnt = (unsigned short)bcnt;
paramSet1.cCnt = (unsigned short)ccnt;
/* Setting up the SRC/DES Index */
paramSet1.srcBIdx = (short)acnt;
paramSet1.destBIdx = 0;
if (syncType == EDMA3_SYNC_A)
{
/* A Sync Transfer Mode */
paramSet1.srcCIdx = (short)0;
paramSet1.destCIdx = (short)0;
}
else
{
/* AB Sync Transfer Mode */
paramSet1.srcCIdx = ((short)acnt * (short)bcnt);
paramSet1.destCIdx = ((short)acnt * (short)bcnt);
}
paramSet1.linkAddr = SIZE_PARAMSET * (PAR_LINK_START + 1); //(unsigned short)0xFFFFu;
paramSet1.bCntReload = (unsigned short)0u;
paramSet1.opt = 0u;
/* Src & Dest are in INCR modes */
paramSet1.opt &= 0xFFFFFFFCu;
/* Program the TCC */
paramSet1.opt |= ((tccNumR << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
paramSet1.opt |= (EDMA3CC_OPT_TCCMOD_EARLY << EDMA3CC_OPT_TCCMOD_SHIFT);

/* Enable Intermediate & Final transfer completion chaining */
paramSet1.opt |= (1 << EDMA3CC_OPT_ITCCHEN_SHIFT);
paramSet1.opt |= (1 << EDMA3CC_OPT_TCCHEN_SHIFT);

if (syncType == EDMA3_SYNC_A)
{
paramSet1.opt &= 0xFFFFFFFBu;
}
else
{
/* AB Sync Transfer Mode */
paramSet1.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
}

/* Now, write the PaRAM Set. */
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNumT, &paramSet1);
// write link param set into memory
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, (PAR_LINK_START + 1), &paramSet1);
}

/* Request DMA channel and TCC */
retVal = EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
chNumR, tccNumR, evtQ);

/* Channel 4 to MCBSP receiver */
if (TRUE == retVal)
{
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)DRR;
paramSet.destAddr = (unsigned int)&ADCIN;

paramSet.aCnt = (unsigned short)acnt;
paramSet.bCnt = (unsigned short)bcnt;
paramSet.cCnt = (unsigned short)ccnt;
/* Setting up the SRC/DES Index */
paramSet.srcBIdx = 0;
paramSet.destBIdx = (short)acnt;
if (syncType == EDMA3_SYNC_A)
{
/* A Sync Transfer Mode */
paramSet.srcCIdx = (short)0;
paramSet.destCIdx = (short)0;
}
else
{
/* AB Sync Transfer Mode */
paramSet.srcCIdx = ((short)acnt * (short)bcnt);
paramSet.destCIdx = ((short)acnt * (short)bcnt);
}
paramSet.linkAddr = SIZE_PARAMSET * (PAR_LINK_START); //(unsigned short)0xFFFFu;
paramSet.bCntReload = (unsigned short)0u;
paramSet.opt = 0u;
/* Src & Dest are in INCR modes */
paramSet.opt &= 0xFFFFFFFCu;
/* Program the TCC */
paramSet.opt |= ((tccNumR << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); //Chained DMA Channel 5

/* Enable Intermediate & Final transfer completion chaining */
// paramSet.opt |= (1 << EDMA3CC_OPT_ITCCHEN_SHIFT);
// paramSet.opt |= (1 << EDMA3CC_OPT_TCCHEN_SHIFT);

if (syncType == EDMA3_SYNC_A)
{
paramSet.opt &= 0xFFFFFFFBu;
}
else
{
/* AB Sync Transfer Mode */
paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
}

/* Now, write the PaRAM Set. */
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNumR, &paramSet);
// write link param set into memory
EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, (PAR_LINK_START), &paramSet);
}

// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNumR, EDMA3_TRIG_MODE_EVENT);

EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNumT, EDMA3_TRIG_MODE_EVENT); //use MCBSP Receive event to trigger the ADC write and read

}