This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM623: How user can assert TX_EN

Part Number: AM623
Other Parts Discussed in Thread: SK-AM62

Hello,

Let me confirm about below.

* I would like you to confirm how user can assert TX_EN for RMII interface.
I'm checking description on TRM, it seems that there is no information about this.
Could you please confirm ?

Best Regards,

  • Hello Ryuuichi machida,

    Thank you for the query.

    I would expect the TX_EN for RMII interface to be enabled as part of the data interface protocol.

    I am not sure i understand your question on user asserting TX_EN.

    Please elaborate your query.

    Regards,

    Sreenivasa

  • Hello,

    I would like you to confirm about detail of following description.

    >I would expect the TX_EN for RMII interface to be enabled as part of the data interface protocol.
    Do you mean when user send packet to TX buffer, TX_EN is automatically genearted ?

    Best Regards,

  • Hello Ryuuichi machida,

    Thank you.

    I extracted the description from an app note referenced below..

    3.5 TX_EN - Transmit Enable
    TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. TX_EN shall be asserted
    synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be
    transmitted are presented. The MAC should assert TX_EN negated prior to the first REF_CLK rising edge
    following the final di-bit of a frame.
    TX_EN shall transition synchronously with respect to REF_CLK.
    https://www.ti.com/lit/an/snla076a/snla076a.pdf

    Please review the RMII specifications for additional information.

    Regards,

    Sreenivasa

  • Hello,

    Thank you for your reply.

    What I want to know is what behavior should be done(want to know exact procedure) to output TX_EN.
    Could you confirm about above ?

    Best regards,

  • Hello Ryuuichi, machida,

    Thank you.

    I could not find any descrtiption in the TRM that i could share.

    I would assume that the TRM assume customer would be referencing the specific interface standards.

    There was a similar question and the EPHY team reference the below link for the standard that you could use.

    RMII consortium specification

    Could you please help me understand the context of the query for me to support better.

    Regards,

    Sreenivasa

  • Hello,

    Thank you for your reply.

    - 1 -
    https://e2e.ti.com/support/interface-group/interface---internal/f/interface---internal-forum/1249761/rmii-consortium-specification/4729448#4729448

    I'm sorry I can not access above URL.
    It seems that this is TI internal site, can you extract the point ?

    - 2 -
    >Could you please help me understand the context of the query for me to support better.
    Now, we have problem on case of RMII.
    Customer create custom board with RMII PHY and connect AM623. The SDK condition is Linux SDK(ver 08_05_00_21).

    The problem of above is user can not observe TX_EN when they send packet from AM62.(Wh have already confirmed "link up".)
    If you would like to know detail and need detail discussion, please let me communicate internally.

    However, above is the reason why we want to know how user can output TX_EN.

    Best Regards,

  • Hello Ryuuichi, machida,

    Thank you.


    I'm sorry I can not access above URL.
    It seems that this is TI internal site, can you extract the point ?

    The RMII standard can be found here: http://ebook.pldworld.com/_eBook/-Telecommunications,Networks-/TCPIP/RMII/rmii_rev12.pdf

    Customer create custom board with RMII PHY and connect AM623.

    Could you confirm if the hardware configuration customer made is in line with the recommendations in the data sheet or TRM.

    Would customer be Ok to share the schematics for quick review.

    Regards,

    Sreenivasa

  • Hello,

    Thank you for your reply.

    >The RMII standard can be found here: http://ebook.pldworld.com/_eBook/-Telecommunications,Networks-/TCPIP/RMII/rmii_rev12.pdf
    It seems that this URL has already invalid. (I could not jump pdf page.)

    >Would customer be Ok to share the schematics for quick review.
    Could you give your email address ? I would share it internally.

    Best regards,

  • Hello Ryuuichi, machida,

    Thank you.

    You could use the attached for quick reference.

    RMII TM Specification.pdf

    Please send a private message.

    Regards,

    Sreenivasa

  • Hello,

    Thank you for your reply.
    I sent schematic info which is related to ethernet to private message.
    Please let us discuss this on private message.

    Best Regards,

  • Hello Ryuuichi, machida,

    Thanks. there was a planned maintenance shutdown of E2E on Thursday and Friday.

    Let me review the inputs and reply.

    Regards,

    Sreenivasa

  • Hello Ryuuichi, machida,

    Trying to understand the note.

    Please let us discuss this on private message.

    Did you mean we do the discussion also as private message.

    Regards,

    Sreenivasa

  • Hello,

    Thank you for your reply.

    Yes, you are correct. Maybe we include customer information, so please discuss on private message. Please understand my situation.

    Best Regards,

  • Hello Ryuuichi, machida,

    Thank you for the note and understand.

    Will continue the conversation over private message.

    Regards,

    Sreenivasa

  • Hello Schuyler

    I added the below input i received from  Ryuuichi, machida,

    Can you please check with customer on the RMII driver they are using. Was this modified by customer? How was the driver verified?
    I heard that customer use kernel standard RMII driver which are included in Linux SDK (Ver 08_06_00_45).

    Regards,

    Sreenivasa

  • Hi,

    I need to ask a few starter questions, I am assuming that Linux is being used.

    Assuming the port is eth0 please attach the results of the following commands:

    - ifconfig eth0

    - ethtool eth0

    - ethtool -S eth0

    Best Regards,

    Schuyler

  • Hello Ryuuichi, machida,

    I see a similar query below 

    (+) AM623: Cannot establish Ethernet RMII data communication(Tx/Rx) between MAC and PHY - Processors forum - Processors - TI E2E support forums

    The issue description is as below. Can you review and confirm if this is the same project and also clarify the issue observed to continue further analysis.

    We have designed Ethernet RMII communication circuit on our new PCB using TI MCU and PHY.
    When Ethernet cable connects from this PCB to PC for the test, link up can be done (100Mbps, Full-duplex) but ping cannot success.

    Parts name of MCU and PHY are the followings.
      MCU: AM6231ASGGGAALW
      PHY: DP83825IRMQR  x2 (eth0, eth1) used as RMII master mode

    We have designed the firmware of Ethernet communication module based on the one for SK-AM62.
    (Changed only some parameters and defines from for RGMII mode to for RMII mode.)

    We have confirmed that the port mode setect of both eth0/eth1 is RMII.
      CTRL_ENET1_CTRL Register (Offset = 4044h) ENET1_CTRL_PORT_MODE_SEL: b001 - RMII
      CTRL_ENET2_CTRL Register (Offset = 4048h) ENET2_CTRL_PORT_MODE_SEL: b001 - RMII
      CTRL_ENET1_CTRL_PROXY Register (Offset = 6044h) ENET1_CTRL_PORT_MODE_SEL_PROXY: b001 - RMII
      CTRL_ENET2_CTRL_PROXY Register (Offset = 6048h) ENET2_CTRL_PORT_MODE_SEL_PROXY: b001 - RMII

    Details of ping NG;
      PC --> PCB: PC send ARP request to PCB(as global packet), but PCB send no response message to PC.
      PCB --> PC: PCB send ARP request to PC(as global packet), then PC send the response message to PCB, but then PCB send ARP request to PC(as global packet) again. It repeats until ping command of PCB is stopped.

    We measured the waveform of main signal lines around PHY.
    The waveforms of MDIO, MDC, 50MHzOut, TD_P/M, RD_P/M has the correct changes and seem no problem.
    But the waveforms of TX_EN, TX_D0, TX_D1, RX_D0, RX_D1, RX_ER, CRS_DV are always 0V with no change.

    Please give us some advice if it can be guessed something suspicious by the above information, or if there are what we need to check more.

    Regards,

    Sreenivasa

  • Hello Sreenuvasa-san and Schuyler-san,

    Thank you for your reply.

    -1-

    - ifconfig eth0

    - ethtool eth0

    - ethtool -S eth0

    => Please see attached file(txt file) about result.
    (Status of "From Line 1 to Line 210" is "Disabled link up" with PC, Status of "From Line 211 to Line 424" is "Enabled link up" with PC.)

    - 2 -
    > Can you review and confirm if this is the same project and also clarify the issue observed to continue further analysis.
    Thank you for your notification.
    Yes, I confirmed with customer and thread which you point out is same as mine.
    I discussed customer and we would like to continue discussion on following customer's thread.
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1269687/am623-cannot-establish-ethernet-rmii-data-communication-tx-rx-between-mac-and-phy

    You asked to customer about schematic information, but this is same one which I shared on private message. So please refer them.

    Therefore, I will close this thread.

    Best Regards,

    eth0_Etternet_E2E.txt
    Fullscreen
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    root@am62xx-evm:~# ifconfig eth0
    eth0 Link encap:Ethernet HWaddr 34:08:E1:87:A8:CA
    UP BROADCAST MULTICAST MTU:1500 Metric:1
    RX packets:0 errors:0 dropped:0 overruns:0 frame:0
    TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
    collisions:0 txqueuelen:1000
    RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
    root@am62xx-evm:~# ethtool eth0
    Settings for eth0:
    Supported ports: [ TP MII ]
    Supported link modes: 10baseT/Half 10baseT/Full
    100baseT/Half 100baseT/Full
    Supported pause frame use: Symmetric
    Supports auto-negotiation: Yes
    Supported FEC modes: Not reported
    Advertised link modes: 10baseT/Half 10baseT/Full
    100baseT/Half 100baseT/Full
    Advertised pause frame use: Symmetric
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     

  • Hello Ryuuichi, machida,

    Thank you for the note.

    You asked to customer about schematic information, but this is same one which I shared on private message. So please refer them.

    It took me some time to realize the queries are for the same project since the issues reported were different.

    Schuyler, 

    In the other thread customer reported there is no clock from the PHY side.

    I will review if there are any issues that can be seen from the hardware side before i assign for you to support.

    Regards,

    Sreenivasa