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Greetings,
We have designed Ethernet RMII communication circuit on our new PCB using TI MCU and PHY.
When Ethernet cable connects from this PCB to PC for the test, link up can be done (100Mbps, Full-duplex) but ping cannot success.
Parts name of MCU and PHY are the followings.
MCU: AM6231ASGGGAALW
PHY: DP83825IRMQR x2 (eth0, eth1) used as RMII master mode
We have designed the firmware of Ethernet communication module based on the one for SK-AM62.
(Changed only some parameters and defines from for RGMII mode to for RMII mode.)
We have confirmed that the port mode setect of both eth0/eth1 is RMII.
CTRL_ENET1_CTRL Register (Offset = 4044h) ENET1_CTRL_PORT_MODE_SEL: b001 - RMII
CTRL_ENET2_CTRL Register (Offset = 4048h) ENET2_CTRL_PORT_MODE_SEL: b001 - RMII
CTRL_ENET1_CTRL_PROXY Register (Offset = 6044h) ENET1_CTRL_PORT_MODE_SEL_PROXY: b001 - RMII
CTRL_ENET2_CTRL_PROXY Register (Offset = 6048h) ENET2_CTRL_PORT_MODE_SEL_PROXY: b001 - RMII
Details of ping NG;
PC --> PCB: PC send ARP request to PCB(as global packet), but PCB send no response message to PC.
PCB --> PC: PCB send ARP request to PC(as global packet), then PC send the response message to PCB, but then PCB send ARP request to PC(as global packet) again. It repeats until ping command of PCB is stopped.
We measured the waveform of main signal lines around PHY.
The waveforms of MDIO, MDC, 50MHzOut, TD_P/M, RD_P/M has the correct changes and seem no problem.
But the waveforms of TX_EN, TX_D0, TX_D1, RX_D0, RX_D1, RX_ER, CRS_DV are always 0V with no change.
Please give us some advice if it can be guessed something suspicious by the above information, or if there are what we need to check more.
Thanks,
Nakashima
Hello Mr. Sreenivasa,
Thanks for your reply.
>>Are all the power supplies as expected including supply ramp.
Yes, as far as we have confirmed.
I attach the schematic diagram of Ethernet circuit between AM6231 and DP83825IRMQR as followings.
Please confirm the details.
<Around AM623>
<Around PHY (RMII0(eth0) side)>
<Around PHY (RMII1(eth1) side)>
Thanks,
Nakashima
Hello Nakashima,
Could you conform the implementation in the design is as below - MCU_PORz is not connected.
Regards,
Sreenivasa
Hello Nakashima,
I am assuming some of the nets were deleted while providing the schematics and not able to trace the implementation.
EX: 25M SoC clock is not visible. LFOSC0 is not connected. When not used Xi needs to be terminated. WKUP_I2c0 is not terminated. This needs to be terminated irrespective of the use case.
Verify the below section of the DP83825i data sheet
6.6 Timing Requirements
Follow the AM625 for the reset implementation.
Use either RESETSTSTz or PORz_OUT. the IO needs to be pulled up to strap the Ethernet configuration during poweer-up.
Please review the schematics with respect to SK for any additional errors and verify the EPHY clock input and reset requirements as per data sheet are followed.
Regards,
Sreenivasa
Hello Sreenivasa-san,
Thanks for your reply.
I confirmed the EPHY output (RX; RX_D0, RX_D0, RX_ER, CRS_DV) when the EPHY power up and configured, as your request.
The results are followings.
1) RX_D0 on RMII1(eth1) side raised up from 0V to 3.3V for a moment, but then down to 0V and had never raised up again after it.
2) Other RX outputs on RMII1(eth1) side except for RX_D0 and all RX outputs on RMII0(eth0) side were always 0V before/after EPHY power up.
The latest pull-up/pull-down implementation for straps configuration are the followings, which I shared to you on this thread before.
The behavior of 1) is because only this output line is pull-up, and it can guess that PHY set RX_D0 output to low soon after reading straps configuration was completed.
Best regards,
Nakashima
