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Original question:
TDA4VM: TDA4 DSI interface display failed with vision-app run ./run_app_single_cam.sh.
Hi, TI support team.
Using PSDKLA8.1. So we choose to use DSI interface to output image (superframe: 2*640x480 as 1280x480) in RTOS.
Refer to this case, So we modified the resoluation to 1280x480 in Vision-apps, and replaced Elephant image by using 1280x480 in TI-DL demo.
We made chages: 1. RTOS Driver and 2. Vision-apps.
From 28c8c2592f73f574dfdcaae77f501dee20c1550c Mon Sep 17 00:00:00 2001
From: peifeng.zhang <peifeng.zhang@ecarxgroup.com>
Date: Tue, 14 Feb 2023 15:12:37 +0800
Subject: [PATCH] [BSP] DSI bring-up For DLP Module & update RTOS driver
Change-Id: Ib71f849a41182c799ef52b636b9a24224286a51a
---
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.c
index 6541a5a..605d598 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.c
@@ -128,6 +128,168 @@
return BOARD_SOK;
}
+Board_STATUS Uled_Eviyos_ReadReg(void *handle,
+ uint32_t slaveAddr,
+ uint8_t regAddr,
+ uint32_t *regData,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout)
+{
+ Board_STATUS ret = BOARD_SOK;
+ I2C_Transaction transaction;
+ uint8_t tx[2];
+
+ I2C_Handle i2cHandle = (I2C_Handle)handle;
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &tx[0];
+ transaction.writeCount = 1;
+ transaction.readBuf = NULL;
+ transaction.readCount = 0;
+ transaction.timeout = i2cTimeout;
+
+ /* 16-bit regAddr data to be sent */
+ if(byteOrdSel == BOARD_I2C_REG_ADDR_MSB_FIRST)
+ {
+ tx[0] = (uint8_t)(regAddr & 0xFF);
+ }
+
+ ret = I2C_transfer(i2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ BOARD_DEVICES_ERR_LOG("Failing while transmitting the rd reg addr with error code - %d\n", ret);
+ ret = -1;
+ return ret;
+ }
+
+ transaction.writeBuf = NULL;
+ transaction.writeCount = 0;
+ transaction.readBuf = regData;
+ transaction.readCount = numOfBytes;
+
+ ret = I2C_transfer(i2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ BOARD_DEVICES_ERR_LOG("Failing while reading the register data by returning - %d\n", ret);
+ ret = -1;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+Board_STATUS Board_i2c16BitRegWr16bit(void *handle,
+ uint32_t slaveAddr,
+ uint16_t regAddr,
+ uint16_t *regVal,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t rawRegVal[4];
+
+ I2C_Transaction transaction;
+#if 1
+ if (numOfBytes > 4u) {
+ ret = BOARD_INVALID_PARAM;
+ }
+#endif
+
+ if(BOARD_SOK == ret) {
+ I2C_Handle i2cHandle = (I2C_Handle)handle;
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = rawRegVal;
+ transaction.writeCount = numOfBytes;
+ transaction.readBuf = NULL;
+ transaction.readCount = 0;
+ transaction.timeout = i2cTimeout;
+
+
+ if (byteOrdSel == BOARD_I2C_REG_ADDR_MSB_FIRST) {
+ /* Convert Registers address and value into 8bit array */
+ rawRegVal[0U] = (uint8_t) ((regAddr >> 8U) & (uint8_t) 0xFF);
+ rawRegVal[1U] = (uint8_t) ((regAddr >> 0U) & (uint8_t) 0xFF);
+ rawRegVal[2U] = (uint8_t) ((*regVal >> 8U) & (uint8_t) 0xFF);
+ rawRegVal[3U] = (uint8_t) ((*regVal >> 0U) & (uint8_t) 0xFF);
+ }
+
+ ret = I2C_transfer(i2cHandle, &transaction);
+ printf("ZPF_I2C: %s ret = %d !! \n", __func__, ret);
+
+ if(ret != I2C_STS_SUCCESS) {
+ BOARD_DEVICES_ERR_LOG(
+ "Failing while writing data by returning - %d\n\r", ret);
+ ret = -1;
+ return ret;
+ }
+ }
+
+ return BOARD_SOK;
+}
+
+Board_STATUS Board_i2c8BitRegWr32bit(void *handle,
+ uint32_t slaveAddr,
+ uint8_t regAddr,
+ uint32_t *regVal,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t rawRegVal[6];
+
+ I2C_Transaction transaction;
+#if 0
+ if (numOfBytes > 4u) {
+ ret = BOARD_INVALID_PARAM;
+ }
+#endif
+
+ if(BOARD_SOK == ret) {
+ I2C_Handle i2cHandle = (I2C_Handle)handle;
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &rawRegVal[0];
+ transaction.writeCount = numOfBytes;
+ transaction.readBuf = NULL;
+ transaction.readCount = 0;
+ transaction.timeout = i2cTimeout;
+
+ if (byteOrdSel == BOARD_I2C_REG_ADDR_MSB_FIRST) {
+ /* Convert Registers address and value into 8bit array */
+ rawRegVal[0U] = (uint8_t) ((regAddr >> 8U) & (uint8_t) 0xFF);//Need_test 16-bit OR 8-bit regAddr
+ rawRegVal[1U] = (uint8_t) ((regAddr >> 0U) & (uint8_t) 0xFF);
+
+ rawRegVal[2U] = (uint8_t) ((*regVal >> 24U) & (uint8_t) 0xFF);
+ rawRegVal[3U] = (uint8_t) ((*regVal >> 16U) & (uint8_t) 0xFF);
+ rawRegVal[4U] = (uint8_t) ((*regVal >> 8U) & (uint8_t) 0xFF);
+ rawRegVal[5U] = (uint8_t) ((*regVal >> 0U) & (uint8_t) 0xFF);
+ }
+
+ ret = I2C_transfer(i2cHandle, &transaction);
+ //printf("ZPF_I2C: %s ret = %d !! \n", __func__, ret);
+
+ if(ret != I2C_STS_SUCCESS) {
+ BOARD_DEVICES_ERR_LOG(
+ "Failing while writing data by returning - %d\n\r", ret);
+ ret = -1;
+ }
+ }
+ return BOARD_SOK;
+}
+
/**
* \brief I2C 16-bit register write fuunction
*
@@ -186,9 +348,10 @@
tx[0] = (uint8_t)(regAddr & 0x00FF);
tx[1] = (uint8_t)((regAddr & 0xFF00) >> 8);
}
-
- txPtr = &tx[2];
+
+ txPtr = &tx[2];
/* regData to be sent */
+ //printf("ZPF_I2C: Ready to send !! \n");
while(numOfBytes)
{
*txPtr = *regData;
@@ -198,6 +361,7 @@
}
ret = I2C_transfer(i2cHandle, &transaction);
+ //printf("ZPF_I2C: %s ret = %d !! \n", __func__, ret);
if(ret != I2C_STS_SUCCESS)
{
BOARD_DEVICES_ERR_LOG(
@@ -474,3 +638,4 @@
}
return 0;
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.h b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.h
index 391fda9..0ec1fa2 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.h
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.h
@@ -243,6 +243,35 @@
uint8_t byteOrdSel,
uint32_t i2cTimeout);
+/*
+ * @ Description: Added by zhangpeifeng
+ * Just for DLP POC.
+ *
+ */
+Board_STATUS Board_i2c16BitRegWr16bit(void *handle,
+ uint32_t slaveAddr,
+ uint16_t regAddr,
+ uint16_t *regData,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout);
+
+Board_STATUS Board_i2c8BitRegWr32bit(void *handle,
+ uint32_t slaveAddr,
+ uint8_t regAddr,
+ uint32_t *regVal,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout);
+
+Board_STATUS Uled_Eviyos_ReadReg(void *handle,
+ uint32_t slaveAddr,
+ uint8_t regAddr,
+ uint32_t *regData,
+ uint8_t numOfBytes,
+ uint8_t byteOrdSel,
+ uint32_t i2cTimeout);
+
/**
* \brief I2C 8-bit register read function
*
@@ -340,3 +369,4 @@
#endif /* _COMMON_H_ */
/* @} */
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c
index a63dc62..a7c2710 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c
@@ -1468,7 +1468,7 @@
if(FVID2_SOK != retVal)
{
- GT_0trace(DssTrace, GT_ERR, "Set DSS parameter IOCTL failed\r\n");
+ GT_0trace(DssTrace, GT_ERR, "ZPF: Set DSS parameter IOCTL failed\r\n");
}
/* Post the instance semaphore */
@@ -1851,11 +1851,22 @@
((dispParams->pipeCfg.outHeight + dispParams->layerPos.startY) >
instObj->dispHeight))
{
- GT_0trace(DssTrace,
+ GT_6trace(DssTrace,
GT_ERR,
- "Input width+startX/height+startY > display width/height\r\n");
+ "Input width+startX/height+startY > display width/height\r\n \
+ dispParams->pipeCfg.outWidth = %d + dispParams->layerPos.startX = %d instObj->dispWidth = %d\r\n \
+ dispParams->pipeCfg.outHeight = %d + dispParams->layerPos.startY = %d instObj->dispHeight = %d\r\n", \
+ dispParams->pipeCfg.outWidth, dispParams->pipeCfg.outWidth + dispParams->layerPos.startX, instObj->dispWidth, \
+ dispParams->pipeCfg.outHeight, dispParams->pipeCfg.outHeight + dispParams->layerPos.startY, instObj->dispHeight);
//retVal = FVID2_EINVALID_PARAMS;
}
+ GT_6trace(DssTrace,
+ GT_ERR,
+ "[ZPF] Input width+startX/height+startY >=< display width/height\r\n \
+ dispParams->pipeCfg.outWidth = %d + dispParams->layerPos.startX = %d instObj->dispWidth = %d\r\n \
+ dispParams->pipeCfg.outHeight = %d + dispParams->layerPos.startY = %d instObj->dispHeight = %d\r\n", \
+ dispParams->pipeCfg.outWidth, dispParams->pipeCfg.outWidth + dispParams->layerPos.startX, instObj->dispWidth, \
+ dispParams->pipeCfg.outHeight, dispParams->pipeCfg.outHeight + dispParams->layerPos.startY, instObj->dispHeight);
/* Interlaced to progressive or vice versa*/
if(dispParams->pipeCfg.inFmt.scanFormat != instObj->dispScanFormat)
@@ -1886,6 +1897,7 @@
GT_ERR,
"Downscaling ratio is more than 0.25x \r\n");
retVal = FVID2_EINVALID_PARAMS;
+
}
if((dispParams->pipeCfg.inFmt.height != dispParams->pipeCfg.outHeight) ||
@@ -2143,3 +2155,4 @@
return isFarFromVsync;
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_multi_cam/main.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_multi_cam/main.c
index a7a7020..475a26e 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_multi_cam/main.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_multi_cam/main.c
@@ -812,24 +812,24 @@
if (status == VX_SUCCESS)
{
obj->displayObj1.disp_params.pipeId = 0;
- obj->displayObj1.disp_params.outWidth = 1920;
+ obj->displayObj1.disp_params.outWidth = 960;
obj->displayObj1.disp_params.outHeight = 1080;
obj->displayObj1.disp_params.posX = 0;
- obj->displayObj1.disp_params.posY = 0;
+ obj->displayObj1.disp_params.posY = 1080;
status = app_init_display(obj->context, &obj->displayObj1, "display_obj1");
- APP_PRINTF("Display init done!\n");
+ APP_PRINTF("Left Display init done!\n");
}
if (status == VX_SUCCESS)
{
//status = app_init_display(obj->context, &obj->displayObj, "display_obj");
obj->displayObj2.disp_params.pipeId = 2;
- obj->displayObj2.disp_params.outWidth = 1920;
+ obj->displayObj2.disp_params.outWidth = 960;
obj->displayObj2.disp_params.outHeight = 1080;
- obj->displayObj2.disp_params.posX = 1920;
- obj->displayObj2.disp_params.posY = 0;
+ obj->displayObj2.disp_params.posX = 960;
+ obj->displayObj2.disp_params.posY = 1080;
status = app_init_display(obj->context, &obj->displayObj2, "display_obj2");
- APP_PRINTF("Display init done!\n");
+ APP_PRINTF("Right Display init done!\n");
}
appPerfPointSetName(&obj->total_perf , "TOTAL");
@@ -1453,3 +1453,4 @@
vxAddParameterToGraph(graph, parameter);
vxReleaseParameter(¶meter);
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_single_cam/app_single_cam_main.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_single_cam/app_single_cam_main.c
index 3b0216b..0e113b5 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_single_cam/app_single_cam_main.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_single_cam/app_single_cam_main.c
@@ -252,9 +252,9 @@
/* Display initialization */
memset(&obj->display_params, 0, sizeof(tivx_display_params_t));
obj->display_params.opMode = TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE;
- obj->display_params.pipeId = 2;
- obj->display_params.outHeight = 1080;
- obj->display_params.outWidth = 1920;
+ obj->display_params.pipeId = 0;
+ obj->display_params.outHeight = 640;//1080;
+ obj->display_params.outWidth = 480;//1920;
obj->display_params.posX = 0;
obj->display_params.posY = 0;
@@ -724,8 +724,8 @@
}
else
{
- obj->display_params.posX = (1920U - obj->display_params.outWidth)/2;
- obj->display_params.posY = (1080U - obj->display_params.outHeight)/2;
+ obj->display_params.posX = 0;//(1920U - obj->display_params.outWidth)/2;
+ obj->display_params.posY = 0;//(1080U - obj->display_params.outHeight)/2;
obj->display_param_obj = vxCreateUserDataObject(obj->context, "tivx_display_params_t", sizeof(tivx_display_params_t), &obj->display_params);
obj->displayNode = tivxDisplayNode(obj->graph, obj->display_param_obj, obj->display_image);
}
@@ -1710,3 +1710,4 @@
return status;
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/modules/src/app_display_module.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/modules/src/app_display_module.c
index e44f2e7..733222a 100644
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/modules/src/app_display_module.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/modules/src/app_display_module.c
@@ -96,18 +96,18 @@
if (dispId == 0)
{
displayObj->disp_params.pipeId = 0; /* pipe ID = 2 */
- displayObj->disp_params.outWidth = 1920;
- displayObj->disp_params.outHeight = 1080;
+ displayObj->disp_params.outWidth = 640;//960;
+ displayObj->disp_params.outHeight = 480;//1080;
displayObj->disp_params.posX = 0;
displayObj->disp_params.posY = 0;
}
else
{
displayObj->disp_params.pipeId = 2; /* pipe ID = 2 */
- displayObj->disp_params.outWidth = 1920;
- displayObj->disp_params.outHeight = 1080;
- displayObj->disp_params.posX = 1920;
- displayObj->disp_params.posY = 0;
+ displayObj->disp_params.outWidth = 640;//960;
+ displayObj->disp_params.outHeight = 480;//1080;
+ displayObj->disp_params.posX = 640;//1280;
+ displayObj->disp_params.posY = 0;//80;
}
displayObj->disp_params_obj = vxCreateUserDataObject(context, "tivx_display_params_t", sizeof(tivx_display_params_t), &displayObj->disp_params);
@@ -162,3 +162,4 @@
}
return status;
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c
index 806079d..a2e31fe 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c
@@ -541,20 +541,39 @@
#ifdef ENABLE_DSS_DSI
prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
- //prm.timings.width = 1280U;
- //prm.timings.height = 800U;
- prm.timings.width = 1920U;
- prm.timings.height = 1080U;
- prm.timings.hFrontPorch = 160U;
- prm.timings.hBackPorch = 100U;
- prm.timings.hSyncLen = 80U;
- prm.timings.vFrontPorch = 5U;
- prm.timings.vBackPorch = 5U;
- prm.timings.vSyncLen = 5U;
- //prm.timings.pixelClock = 274626000ULL;
- //prm.timings.pixelClock = 190530000ULL;
+ //prm.timings.width = 2560U;
+ //prm.timings.height = 1080U;
+ //prm.timings.width = 3840U;
+ //prm.timings.width = 1920U;
+ //prm.timings.height = 1080U;
+ prm.timings.width = 1280U;//640 * 2 = 1280
+ prm.timings.height = 480U;
+
+ //prm.timings.hFrontPorch = 320U;//160U;
+ //prm.timings.hFrontPorch = 160U;
+ prm.timings.hFrontPorch = 32U;//16U;
+ //prm.timings.hBackPorch = 200U;//100U;
+ //prm.timings.hBackPorch = 100U;
+ prm.timings.hBackPorch = 96U;//48U;
+ //prm.timings.hSyncLen = 160U;//80U;
+ //prm.timings.hSyncLen = 80U;
+ prm.timings.hSyncLen = 192U;//96U;
+
+ //prm.timings.vFrontPorch = 5U;
+ //prm.timings.vBackPorch = 5U;
+ //prm.timings.vSyncLen = 5U;
+ prm.timings.vFrontPorch = 10U;
+ prm.timings.vBackPorch = 33U;
+ prm.timings.vSyncLen = 2U;
+
+ //prm.timings.pixelClock = 274626000ULL;
+ //prm.timings.pixelClock = 190530000ULL;//(2560 + 160 + 100 + 80) * (1080 + 5 + 5 + 5) * 60
//prm.timings.pixelClock = 137313000ULL;
- prm.timings.pixelClock = 148482000ULL;
+ //prm.timings.pixelClock = 148500000ULL;//(1920 + 160 + 100 + 80) * (1080 + 5 + 5 + 5) * 60
+ //prm.timings.pixelClock = 297000000ULL;//(1920*2 + 160*2 + 100*2 + 80*2) * (1080 + 5 + 5 + 5) * 60
+
+ //prm.timings.pixelClock = 25200000ULL;//For DLP Module: (640 + 16 + 48 + 96)800 * (480 + 10 + 33 + 2)525 * 60
+ prm.timings.pixelClock = 50400000ULL;//For DLP Module: (1280 + 32 + 96 + 192)1600 * (480 + 10 + 33 + 2)525 * 60
#endif
status = appDssDefaultInit(&prm);
APP_ASSERT_SUCCESS(status);
@@ -864,3 +883,4 @@
__asm(" IDLE");
#endif
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c
index 79f3894..fe660c2 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c
@@ -536,10 +536,14 @@
{
//dsi_params.numOfLanes = prms->num_lanes;
dsi_params.numOfLanes = 4u;//prms->num_lanes;
- dsi_params.laneSpeedInKbps = 890892u;
- //dsi_params.laneSpeedInKbps = 1143180u;
- //dsi_params.laneSpeedInKbps = 1647756u;
- appLogPrintf("DCTRL: ERROR: zpf_setting numOfLanes = %d, lane-Tx-rate = %ld !!!\n", dsi_params.numOfLanes, dsi_params.laneSpeedInKbps);
+ //dsi_params.laneSpeedInKbps = 890892u;//(1920 + 160 + 100 + 80)2260 * (1080 + 5 + 5 +5)1095 * 60 * 24 / 4
+
+ //dsi_params.laneSpeedInKbps = 151200u;//(640 + 16 + 48 + 96)800 * (480 + 10 + 33 + 2)525 * 60 * 24 / 4
+ dsi_params.laneSpeedInKbps = 302400u;//(1280 + 32 + 96 + 192)1600 * (480 + 10 + 33 + 2)525 * 60 * 24 / 4
+
+ //dsi_params.laneSpeedInKbps = 1143180u;//(2560 + 160 + 100 + 80) * (1080 + 5 + 5 + 5) * 60 * 24 / 4 per-lane
+ //dsi_params.laneSpeedInKbps = 1781784u;//(1920*2 + 160*2 + 100*2 + 80*2) * (1080 + 5 + 5 +5) * 24 / 4 lane-speed
+ appLogPrintf("DCTRL: zpf_setting numOfLanes = %d, lane-Tx-rate = %ld !!!\n", dsi_params.numOfLanes, dsi_params.laneSpeedInKbps);
retVal = Fvid2_control(handle, IOCTL_DSS_DCTRL_SET_DSI_PARAMS,
&dsi_params, NULL);
@@ -547,3 +551,4 @@
return (retVal);
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c
index 15b2486..8dbb2c3 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c
@@ -148,7 +148,7 @@
if (prm->display_type == APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
{
- //appDssConfigureUB941AndUB925(prm);
+ appDssConfigureUB941AndUB925(prm);
}
appDssInitParamsInit(&dssParams);
@@ -350,6 +350,7 @@
/* Only two lanes output supported for AOU LCD */
dsiParams.num_lanes = 4u;
retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_DSI_PARAMS, &dsiParams, sizeof(app_dctrl_dsi_params_t), 0U);
+ //appLogPrintf("ZPF: ERROR: Set DSI params default init failed !!!\n");
}
retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_PATH, &pathInfo, sizeof(pathInfo), 0U);
@@ -380,3 +381,4 @@
return retVal;
}
+
diff --git a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c
index 4529bc0..5ba8aa2 100755
--- a/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c
+++ b/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c
@@ -59,70 +59,245 @@
/* Global Variables */
/* ========================================================================== */
+//#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
+#define BIT8_ADDR 0
+#define BIT16_ADDR 1
+
+typedef struct Board_I2cReg
+{
+ /** GMSL slave address */
+ uint8_t clientAddr;
+ /** regAddr bit */
+ uint8_t regAddrBit;
+ /** GMSL register offset address */
+ uint16_t regAddr;
+ /** GMSL register data */
+ uint8_t regData;
+ /** GMSL i2c delay in milliseconds */
+ uint8_t i2cDelay;
+} Board_I2cReg_t;
+
static I2C_Handle gI2cHandle = NULL;
+static Board_I2cReg_t *g_Board_I2cReg_t_ptr = NULL;
-uint8_t Ub941Ub925Config[][4] = {
-{0x16, 0x01, 0x0A, 0x5},
-{0x16, 0x03, 0x9A, 0x5},
-{0x16, 0x17, 0x9E, 0x5},
-{0x16, 0x07, 0x58, 0x5},
-{0x16, 0x08, 0x22, 0x5},
-{0x16, 0x70, 0x80, 0x5},
-{0x16, 0x77, 0x24, 0x5},
-
-
-{0x16, 0x01, 0x08, 0x5},
-{0x16, 0x1E, 0x01, 0x5},
-{0x16, 0x03, 0x9A, 0x5},
-{0x16, 0x03, 0x9A, 0x5},
-{0x16, 0x03, 0x9A, 0x5},
-{0x16, 0x40, 0x04, 0x5},
-{0x16, 0x40, 0x05, 0x5},
-{0x16, 0x41, 0x21, 0x5},
-{0x16, 0x42, 0x60, 0x5},
-{0x16, 0x40, 0x09, 0x5},
-{0x16, 0x40, 0x09, 0x5},
-{0x16, 0x41, 0x21, 0x5},
-{0x16, 0x42, 0x60, 0x5},
-{0x16, 0x5b, 0x85, 0x5},
-{0x16, 0x4f, 0x8c, 0x5},
-{0x16, 0x4f, 0x84, 0x5},
-{0x16, 0x40, 0x05, 0x5},
-{0x16, 0x40, 0x04, 0x5},
-{0x16, 0x41, 0x05, 0x5},
-{0x16, 0x42, 0x16, 0x5},
-{0x16, 0x40, 0x08, 0x5},
-{0x16, 0x40, 0x08, 0x5},
-{0x16, 0x41, 0x05, 0x5},
-{0x16, 0x42, 0x0c, 0x5},
-{0x16, 0x01, 0x00, 0x5},
-{0x16, 0x66, 0x03, 0x5},
-{0x16, 0x67, 0x03, 0x5},
-{0x16, 0x65, 0x01, 0x5},
-{0x16, 0x64, 0x00, 0x5},
-{0x16, 0x64, 0x04, 0x5},
-
-
-{0x27, 0x00, 0xFE, 0x5},
-
-{0x11, 0x1D, 0x28, 0x5},
-{0x11, 0x1D, 0x29, 0x5},
-
-{0x11, 0x01, 0x06, 0x5},
-{0x11, 0x01, 0x04, 0x5},
-{0x11, 0x03, 0xf0, 0x5},
-{0x11, 0x03, 0xf0, 0x5},
-{0x11, 0x03, 0xf8, 0x5},
-{0x11, 0x29, 0x00, 0x5},
-{0x11, 0x29, 0x00, 0x5},
-{0x11, 0x65, 0x00, 0x5},
-{0x11, 0x65, 0x00, 0x5},
-
-{0x12, 0x0C, 0x20, 0x5},
-{0x12, 0x00, 0x01, 0x5},
-{0x12, 0x04, 0xE6, 0x5},
-
+#if 0
+Board_I2cReg_t Ub941Ub925ConfigEviyosTest[] = {
+ //Just DLP Test_Patterns That Verfiy SPB pass-through OK !!!.
+ //Set Port A Lane Mapping
+ {0x40, BIT16_ADDR, 0x0404 ,0x43, 0x5},
+ //Set Port B Lane Mapping
+ {0x40, BIT16_ADDR, 0x0604 ,0x43, 0x5},
+ //Set GMSL type
+ {0x40, BIT16_ADDR, 0x044D ,0x80, 0x5},
+ //Set BWS DRS DBL Phy A
+ {0x40, BIT16_ADDR, 0x064D ,0x80, 0x5},
+ //Access to LinkA & Change DES0 addr as 0xB0 >> 1 = 0x58
+ {0x40, BIT16_ADDR, 0x0004 ,0x12, 0x5},
+ {0x5A, BIT8_ADDR, 0x01 ,0xB0, 0x5},
+ //Access to LinkB & Change DES1 addr as 0xB4 >> 1 = 0x5A
+ {0x40, BIT16_ADDR, 0x0004 ,0x22, 0x5},
+ {0x5A, BIT8_ADDR, 0x01 ,0xB4, 0x5},
+ //LinkA & B both Enabled
+ {0x40, BIT16_ADDR, 0x0004 ,0x32, 0x5}
};
+#endif
+
+#if 1
+Board_I2cReg_t Ub941Ub925Config[] = {
+ /*
+ * @ Description: MAX96789 + MAX96706 Settings For DLP RGB8
+ * Superframe For 640*2 x 480
+ * 2022-10-25
+ *
+ */
+ //Symmetric 7_13_15-34 Using MAX96789/91/F (GMSL-1/2)
+
+ //#Write TX Enable Y
+ {0x40, BIT16_ADDR, 0x0002, 0x73, 0x05},
+ //#Set Port A Lane Mapping
+ {0x40, BIT16_ADDR, 0x0332, 0x4E, 0x05},
+ //#Set Port B Lane Mapping
+ {0x40, BIT16_ADDR, 0x0333, 0xE4, 0x05},
+ //#Set GMSL type
+ {0x40, BIT16_ADDR, 0x0004, 0x32, 0x05},
+ //#Set BWS DRS DBL Phy A
+ {0x40, BIT16_ADDR, 0x0407, 0x00, 0x05},
+ //#Set BWS DRS DBL Phy B
+ {0x40, BIT16_ADDR, 0x0607, 0x00, 0x05},
+ //#Set oLDI/VESA format phy A
+ {0x40, BIT16_ADDR, 0x0415, 0x01, 0x05},
+ //#Set oLDI/VESA format phy B
+ {0x40, BIT16_ADDR, 0x0615, 0x01, 0x05},
+ //#Clock Select
+ {0x40, BIT16_ADDR, 0x0308, 0x5C, 0x05},
+ //#Start DSI Port
+ {0x40, BIT16_ADDR, 0x0311, 0x03, 0x05},
+ //#Number of Lanes
+ {0x40, BIT16_ADDR, 0x0331, 0x03, 0x05},
+ //#Set phy_config
+ {0x40, BIT16_ADDR, 0x0330, 0x06, 0x05},
+#if 0
+ //#Set soft_dtx_en
+ {0x40, BIT16_ADDR, 0x031C, 0x98, 0x05},
+ //#Set soft_dtx
+ {0x40, BIT16_ADDR, 0x0321, 0x24, 0x05},
+ //#Set soft_dty_en
+ {0x40, BIT16_ADDR, 0x031D, 0x98, 0x05},
+ //#Set soft_dty_
+ {0x40, BIT16_ADDR, 0x0322, 0x24, 0x05},
+#endif
+ //#Default
+ {0x40, BIT16_ADDR, 0x0326, 0xE4, 0x05},
+ //#SSPLL_ODIV_EXP
+ {0x40, BIT16_ADDR, 0x056E, 0x09, 0x05},
+ //#SSPLL_ODIV_EXP
+ {0x40, BIT16_ADDR, 0x056F, 0x1A, 0x05},
+ //#SSPLL_FORCE_DIV/SSPLL_FB_DIV_H
+ {0x40, BIT16_ADDR, 0x0570, 0x40, 0x05},
+ //#CSI_SSPLL_FB_FRACTION_IN_L
+ {0x40, BIT16_ADDR, 0x055B, 0x55, 0x05},
+ //#CSI_SSPLL_FB_FRACTION_IN_H
+ {0x40, BIT16_ADDR, 0x055C, 0x05, 0x05},
+ //#SSPLL_ODIV_EXP
+ {0x40, BIT16_ADDR, 0x0571, 0x09, 0x05},
+ //#SSPLL_FB_DIV_L
+ {0x40, BIT16_ADDR, 0x0572, 0x1A, 0x05},
+ //#SSPLL_FORCE_DIV/SSPLL_FB_DIV_H
+ {0x40, BIT16_ADDR, 0x0573, 0x40, 0x05},
+ //#CSI_SSPLL_FB_FRACTION_IN_L
+ {0x40, BIT16_ADDR, 0x056C, 0x55, 0x05},
+ //#CSI_SSPLL_FB_FRACTION_IN_H
+ {0x40, BIT16_ADDR, 0x056D, 0x05, 0x05},
+ //#HSYNC_WIDTH_L
+ {0x40, BIT16_ADDR, 0x0385, 0xC0, 0x05},
+ //#VSYNC_WIDTH_L
+ {0x40, BIT16_ADDR, 0x0386, 0x02, 0x05},
+ //#HSYNC_WIDTH_H/VSYNC_WIDTH_H
+ {0x40, BIT16_ADDR, 0x0387, 0x00, 0x05},
+ //#VFP_L
+ {0x40, BIT16_ADDR, 0x03A5, 0x0A, 0x05},
+ //#VBP_H
+ {0x40, BIT16_ADDR, 0x03A7, 0x02, 0x05},
+ //#VFP_H/VBP_L
+ {0x40, BIT16_ADDR, 0x03A6, 0x10, 0x05},
+ //#VRES_L
+ {0x40, BIT16_ADDR, 0x03A8, 0xE0, 0x05},
+ //#VRES_H
+ {0x40, BIT16_ADDR, 0x03A9, 0x01, 0x05},
+ //#HFP_L
+ {0x40, BIT16_ADDR, 0x03AA, 0x20, 0x05},
+ //#HBP_H
+ {0x40, BIT16_ADDR, 0x03AC, 0x06, 0x05},
+ //#HFP_H/HBP_L
+ {0x40, BIT16_ADDR, 0x03AB, 0x00, 0x05},
+ //#HRES_L
+ {0x40, BIT16_ADDR, 0x03AD, 0x00, 0x05},
+ //#HRES_H
+ {0x40, BIT16_ADDR, 0x03AE, 0x05, 0x05},
+#if 0
+ //#FIFO/DESKEW_EN
+ {0x40, BIT16_ADDR, 0x03A4, 0xC1, 0x05},
+#endif
+ //#Enable Dual View Block Port A
+ {0x40, BIT16_ADDR, 0x032A, 0x07, 0x05},
+ //#Video Pipe Enable
+ {0x40, BIT16_ADDR, 0x0002, 0x73, 0x05},
+#if 0
+ //#Enable splitter mode reset one shot
+ {0x40, BIT16_ADDR, 0x0010, 0x23, 0x05},
+ //#end for RGB888 setting
+#endif
+ //#set crossbar for link A
+ {0x40, BIT16_ADDR, 0x01B8, 0x06, 0x05},
+ {0x40, BIT16_ADDR, 0x01B9, 0x07, 0x05},
+ {0x40, BIT16_ADDR, 0x01BD, 0x1A, 0x05},
+ {0x40, BIT16_ADDR, 0x01C2, 0x18, 0x05},
+ {0x40, BIT16_ADDR, 0x01C3, 0x19, 0x05},
+ //#set crossbar for link B
+ {0x40, BIT16_ADDR, 0x01FB, 0x06, 0x05},
+ {0x40, BIT16_ADDR, 0x01FC, 0x07, 0x05},
+ {0x40, BIT16_ADDR, 0x0200, 0x1A, 0x05},
+ {0x40, BIT16_ADDR, 0x0205, 0x18, 0x05},
+ {0x40, BIT16_ADDR, 0x0206, 0x19, 0x05},
+ //#set HIM
+ {0x40, BIT16_ADDR, 0x044D, 0x80, 0x05},
+ {0x40, BIT16_ADDR, 0x064D, 0x80, 0x05},
+ //#end of setting serializer
+#if 0
+ {0x40, BIT16_ADDR, 0x0404, 0x43, 0x05},
+ {0x40, BIT16_ADDR, 0x0604, 0x43, 0x05},
+ //#Access to link A
+ //#set deserializer on link A
+ //#change deserializer A address as 0xB0
+ {0x40, BIT16_ADDR, 0x0004, 0x12, 0x05},
+ {0x5A, BIT8_ADDR, 0x01, 0xB0, 0x05},
+ //#set BWS
+ {0x5A, BIT8_ADDR, 0x07, 0x00, 0x05},
+ //#Access to link B
+ //#set deserializer on link A
+ //#change deserializer B address as 0x98
+ {0x40, BIT16_ADDR, 0x0004, 0x22, 0x05},
+ {0x5A, BIT8_ADDR, 0x01, 0xB4, 0x05},
+ //#set BWS
+ {0x58, BIT8_ADDR, 0x07, 0x00, 0x05},
+ //#set serializer BWS
+ //#Set BWS DRS DBL Phy A
+ {0x40, BIT16_ADDR, 0x0407, 0x00, 0x05},
+ //#Set BWS DRS DBL Phy B
+ {0x40, BIT16_ADDR, 0x0607, 0x00, 0x05},
+ //#enable video link
+// {0x40, BIT16_ADDR, 0x0404, 0x83, 0x05},
+// {0x40, BIT16_ADDR, 0x0604, 0x83, 0x05},
+#endif
+ //#enable link A/B at GMSL1 mode
+ {0x40, BIT16_ADDR, 0x0004, 0x32, 0x05},
+ //#enable splitter mode
+ {0x40, BIT16_ADDR, 0x0010, 0x23, 0x05}
+ //#end of SERDES setting
+ //#No need to write deserializer
+};
+#endif
+
+uint32_t configEviyos[][4] = {
+ /**
+ * Eviyos Setting & CRC For FPGA verification
+ * High 16-bit for register setting, Low 16-bit for CRC verification.
+ */
+ {0x50, 0x0000, 0x1098F456, 0x5},
+ {0x50, 0x002C, 0xFE0036FD, 0x5},
+ {0x50, 0x001F, 0x0002BA84, 0x5},
+ {0x50, 0x0021, 0x00037401, 0x5},
+ {0x50, 0x001E, 0x0000ADF6, 0x5},
+ {0x50, 0x000F, 0x003C2E7A, 0x5},
+ {0x50, 0x0013, 0x0000EFA7, 0x5},
+ {0x50, 0x0020, 0x00007352, 0x5},
+#if 0
+ {0x50, 0x0000, 0x0000F594, 0x5},
+#endif
+#if 0
+ //Different Test Patterns can Achieved By Writing 0x00 -- 0x07 in Register 0x22
+ {0x50, 0x0022, 0x00010D13, 0x5},//test_pattern 0x1
+ {0x50, 0x0022, 0x00001D32, 0x5},//test_pattern 0x0
+ {0x50, 0x0022, 0x00010D13, 0x5},//test_pattern 0x1
+ {0x50, 0x0022, 0x00023D70, 0x5},//test_pattern 0x2
+ {0x50, 0x0022, 0x00032D51, 0x5},//test_pattern 0x3
+ {0x50, 0x0022, 0x00045DB6, 0x5},//test_pattern 0x4
+ {0x50, 0x0022, 0x00054D97, 0x5},//test_pattern 0x5
+ {0x50, 0x0022, 0x00067DF4, 0x5},//test_pattern 0x6
+ {0x50, 0x0022, 0x00076DD5, 0x5},//test_pattern 0x7
+#endif
+ //{0x50, 0x0022, 0x00010D13, 0x5},//test_pattern 0x1
+ //Enter Test Pattern Mode
+ //{0x50, 0x0001, 0x0007B243, 0x5}
+ //Enter Normal Mode
+ {0x50, 0x0001, 0x0003F2C7, 0x5}
+};
+
+
+
+
+
/* ========================================================================== */
@@ -131,6 +306,14 @@
static int32_t appDssDsiSetBoardMux();
static int32_t appDssDsiInitI2c();
+//static int32_t DispApp_InitI2c();
+static void toConfigEviyos();
+static int32_t Eviyos_ReadReg(I2C_Handle handle,
+ uint8_t clientAddr,
+ uint8_t regAddr,
+ uint32_t *regVal,
+ uint32_t numOfByte,
+ uint32_t numRegs);
/* ========================================================================== */
@@ -267,47 +450,177 @@
}
}*/
-void appDssConfigureUB941AndUB925(app_dss_default_prm_t *prm)
+static int32_t Eviyos_ReadReg(I2C_Handle handle,
+ uint8_t clientAddr,
+ uint8_t regAddr,
+ uint32_t *regVal,
+ uint32_t numOfByte,
+ uint32_t numRegs)
{
- int32_t status;
- uint32_t cnt, clientAddr;
+ int32_t status = -1;
+ static uint8_t I2cByteOrder = BOARD_I2C_REG_ADDR_MSB_FIRST;
+ uint32_t readReg32bit = 0xFFFF;
+ uint32_t count;
- if(prm->display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
- {
- appLogPrintf("DSS: Configuring SERDES ... !!!\n");
- status = appDssDsiSetBoardMux();
-
- if (FVID2_SOK == status)
- {
- status = appDssDsiInitI2c();
+ for (count = 0; count < numRegs; count++) {
+ /* Read a 16-bit value from Eviyos FPGA */
+ status = Uled_Eviyos_ReadReg(handle, clientAddr, regAddr, &readReg32bit, numOfByte, I2cByteOrder, BOARD_I2C_TRANSACTION_TIMEOUT);
+ if (status != 0 ) {
+ appLogPrintf("ZPF_DSS_Eviyos_CHECK_VALUE: Failed to read DLP Eviyos readReg16bit ... !!!\n");
}
-
- if (FVID2_SOK == status)
- {
- for (cnt = 0; cnt < sizeof(Ub941Ub925Config)/4; cnt ++)
- {
- clientAddr = Ub941Ub925Config[cnt][0];
- status = Board_i2c8BitRegWr(
- gI2cHandle, clientAddr, Ub941Ub925Config[cnt][1],
- &Ub941Ub925Config[cnt][2], 1U, BOARD_I2C_TRANSACTION_TIMEOUT);
-
- appLogWaitMsecs((uint32_t)Ub941Ub925Config[cnt][3]);
-
- if (0 != status)
- {
- appLogPrintf("DSS: Write Failed for ClientAddr 0x%x RegAddr 0x%x Value 0x%x !\n",
- clientAddr, Ub941Ub925Config[cnt][1], Ub941Ub925Config[cnt][2]);
- break;
- }
- }
- }
-
- I2C_close(gI2cHandle);
- appLogPrintf("DSS: SERDES Configuration... Done !!!\n");
}
+
+ return (status);
+}
+
+static void toConfigEviyos()
+{
+ uint8_t clientAddr = 0x00;
+ uint16_t regAddr = 0x00;
+ uint32_t regValueRead = 0xFFFFFFFF;
+ uint32_t cnt;
+ uint32_t status = 0;
+
+ appLogPrintf("ZPF_DSS: Start Configuring DLP Eviyos ... !!!\n");
+
+ for (cnt = 0; cnt < ARRAY_SIZE(configEviyos); cnt ++) {
+ clientAddr = (uint8_t)configEviyos[cnt][0];
+
+ status = Board_i2c8BitRegWr32bit(gI2cHandle,
+ clientAddr,//0xA0 >> 1 = 0x50
+ (uint16_t)configEviyos[cnt][1],//Need_test 16-bit regAddr
+ //(uint8_t)configEviyos[cnt][1],//Need_test 8-bit regAddr
+ (uint32_t *)(&configEviyos[cnt][2]),
+ 6U,//"6U" for <16-bit(regAddr) + 32-bit(regData)>
+ BOARD_I2C_REG_ADDR_MSB_FIRST,
+ BOARD_I2C_TRANSACTION_TIMEOUT);
+
+ appLogWaitMsecs((uint32_t)configEviyos[cnt][3]);
+#if 1
+ if (0 != status) {
+ appLogPrintf("ZPF_DSS: Eviyos Write %d: Failed for ClientAddr 0x%x RegAddr 0x%x Value 0x%x ARRAY_SIZE(configEviyos) = %d!\n",
+ cnt, clientAddr, configEviyos[cnt][1], configEviyos[cnt][2], ARRAY_SIZE(configEviyos));
+ break;
+ //continue;
+ }
+#endif
+#if 0
+ Eviyos_ReadReg(gI2cHandle, (uint8_t)configEviyos[cnt][0], (uint8_t)configEviyos[cnt][1], ®ValueRead, 4U, 1);
+ if (status == 0) {
+ appLogPrintf("Eviyos Debug Reg ReadBack Eviyos Addr: 0x%x EviyosRegAddr: 0x%x, Value 0x%x \n", configEviyos[cnt][0], configEviyos[cnt][1], regValueRead);
+ }
+#endif
+ }
+
+ appLogPrintf("ZPF_DSS: Configuring DLP Eviyos Done ... !!!\n");
}
+void appDssConfigureUB941AndUB925(app_dss_default_prm_t *prm)
+{
+ int32_t status;
+ int32_t status1, status2;
+ uint32_t cnt, clientAddr, count;
+ uint8_t rd_back = 0xFF;
+ uint8_t des_rdbk0 = 0xFF, des_rdbk1 = 0xFF;
+ g_Board_I2cReg_t_ptr = Ub941Ub925Config;
+ //g_Board_I2cReg_t_ptr = Ub941Ub925ConfigEviyosTest;
+
+ if(prm->display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DSI) {
+ appLogPrintf("ZPF_DSS: SERDES Configuration... Start !!!\n");
+ status = appDssDsiSetBoardMux();
+
+ if (FVID2_SOK == status) {
+ status = appDssDsiInitI2c();
+ }
+
+ if (FVID2_SOK == status) {
+ //for (cnt = 0; cnt < ARRAY_SIZE(Ub941Ub925ConfigEviyosTest); cnt++) {
+ for (cnt = 0; cnt < ARRAY_SIZE(Ub941Ub925Config); cnt++) {
+ if (g_Board_I2cReg_t_ptr->regAddrBit == BIT16_ADDR) {
+ status = Board_i2c16BitRegWr(gI2cHandle,
+ g_Board_I2cReg_t_ptr->clientAddr,
+ (uint16_t)g_Board_I2cReg_t_ptr->regAddr,
+ (uint8_t *)&(g_Board_I2cReg_t_ptr->regData),
+ 1U, BOARD_I2C_REG_ADDR_MSB_FIRST, BOARD_I2C_TRANSACTION_TIMEOUT);
+
+ appLogWaitMsecs(g_Board_I2cReg_t_ptr->i2cDelay);
+
+ if (0 != status) {
+ appLogPrintf("ZPF_DSS: SERDES Write Failed for ClientAddr 0x%x RegAddr 0x%x Value 0x%x ARRAY_SIZE(array) = %d !\n",
+ //g_Board_I2cReg_t_ptr->clientAddr, g_Board_I2cReg_t_ptr->regAddr, g_Board_I2cReg_t_ptr->regData, ARRAY_SIZE(Ub941Ub925ConfigEviyosTest));
+ g_Board_I2cReg_t_ptr->clientAddr, g_Board_I2cReg_t_ptr->regAddr, g_Board_I2cReg_t_ptr->regData, ARRAY_SIZE(Ub941Ub925Config));
+ break;
+ }
+ } else {
+ Board_i2c8BitRegWr(gI2cHandle,
+ g_Board_I2cReg_t_ptr->clientAddr,
+ (uint8_t)g_Board_I2cReg_t_ptr->regAddr,
+ (uint8_t *)&(g_Board_I2cReg_t_ptr->regData),
+ 1U, BOARD_I2C_TRANSACTION_TIMEOUT);
+
+ appLogWaitMsecs(g_Board_I2cReg_t_ptr->i2cDelay);
+
+ if (0 != status) {
+ appLogPrintf("ZPF_DSS: SERDES Write Failed for ClientAddr 0x%x RegAddr 0x%x Value 0x%x ARRAY_SIZE(array) = %d !\n",
+ //g_Board_I2cReg_t_ptr->clientAddr, g_Board_I2cReg_t_ptr->regAddr, g_Board_I2cReg_t_ptr->regData, ARRAY_SIZE(Ub941Ub925ConfigEviyosTest));
+ g_Board_I2cReg_t_ptr->clientAddr, g_Board_I2cReg_t_ptr->regAddr, g_Board_I2cReg_t_ptr->regData, ARRAY_SIZE(Ub941Ub925Config));
+ break;
+ }
+ }
+#if 0
+ status = Board_i2c16BitRegWr(gI2cHandle,
+ g_Board_I2cReg_t_ptr->clientAddr,
+ (uint16_t)g_Board_I2cReg_t_ptr->regAddr,
+ (uint8_t *)&(g_Board_I2cReg_t_ptr->regData),
+ 1U, BOARD_I2C_REG_ADDR_MSB_FIRST, BOARD_I2C_TRANSACTION_TIMEOUT);
+
+ appLogWaitMsecs(g_Board_I2cReg_t_ptr->i2cDelay);
+
+ if (0 != status) {
+ appLogPrintf("ZPF_DSS: SERDES Write Failed for ClientAddr 0x%x RegAddr 0x%x Value 0x%x ARRAY_SIZE(array) = %d !\n",
+ g_Board_I2cReg_t_ptr->clientAddr, g_Board_I2cReg_t_ptr->regAddr, g_Board_I2cReg_t_ptr->regData, ARRAY_SIZE(Ub941Ub925Config));
+ break;
+ }
+#endif
+#if 1 //For debug Read SER
+ status1 = Board_i2c16BitRegRd(gI2cHandle,
+ g_Board_I2cReg_t_ptr->clientAddr,
+ (uint16_t)g_Board_I2cReg_t_ptr->regAddr,
+ &rd_back,
+ 1U, BOARD_I2C_REG_ADDR_MSB_FIRST, BOARD_I2C_TRANSACTION_TIMEOUT);
+
+ if (0 == status1) {
+ appLogPrintf("ZPF_DSS: SER Read Back from ClientAddr 0x%x RegAddr 0x%04x Value 0x%04x!\n",
+ g_Board_I2cReg_t_ptr->clientAddr, (uint16_t)g_Board_I2cReg_t_ptr->regAddr, (rd_back & 0xFF));
+ } else {
+ appLogPrintf("ZPF_DSS: SER Failed Read Back from ClientAddr 0x%x RegAddr 0x%04x Value 0x%04x status1 = %d!\n",
+ g_Board_I2cReg_t_ptr->clientAddr, (uint16_t)g_Board_I2cReg_t_ptr->regAddr, (rd_back & 0xFF), status1);
+ }
+
+#endif
+ g_Board_I2cReg_t_ptr++;
+ }
+#if 0 //For debug read DES
+ status2 = Board_i2c8BitRegRd(gI2cHandle, 0x5A, 0x01, &des_rdbk0, 1U, BOARD_I2C_TRANSACTION_TIMEOUT);
+ if ( 0 == status2) {
+ appLogPrintf("DES_ReadBack1 ZPF_DSS: Read Back from DesAddr1: 0x5A RegAddr: 0x01 Value: 0x%x !\n", (des_rdbk0 & 0xFF));
+ }
+ status2 = Board_i2c8BitRegRd(gI2cHandle, 0x58, 0x01, &des_rdbk1, 1U, BOARD_I2C_TRANSACTION_TIMEOUT);
+ if ( 0 == status2) {
+ appLogPrintf("DES_ReadBack2 ZPF_DSS: Read Back from DesAddr2: 0x58 RegAddr: 0x01 Value: 0x%x !\n", (des_rdbk1 & 0xFF));
+ }
+#endif
+
+ appLogPrintf("ZPF_DSS: SERDES Configuration... Done !!!\n");
+
+ toConfigEviyos();
+ I2C_close(gI2cHandle);
+ }
+ }
+}
+
+#if 1
static int32_t appDssDsiSetBoardMux()
{
Board_I2cInitCfg_t i2cCfg;
@@ -317,7 +630,8 @@
i2cCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
i2cCfg.enableIntr = false;
Board_setI2cInitConfig(&i2cCfg);
-
+ SET_DEVICE_STATE_ON(TISCI_DEV_I2C1);
+#if 0
/* Enable DSI in IO Expander */
Board_i2cIoExpInit();
@@ -346,16 +660,22 @@
PIN_NUM_2,
GPIO_SIGNAL_LEVEL_HIGH);
Board_i2cIoExpDeInit();
-
+#endif
return (FVID2_SOK);
}
+#endif
static int32_t appDssDsiInitI2c()
{
int32_t status = FVID2_SOK;
uint8_t domain, i2cInst, slaveAddr;
+ //uint8_t domain = BOARD_SOC_DOMAIN_MAIN;
+ //uint8_t i2cInst = 1U;
+ //uint8_t slaveAddr = 0x40; //0x80 >> 1
I2C_Params i2cParams;
+
+ //DispApp_InitI2c();
/* Initializes the I2C Parameters */
I2C_Params_init(&i2cParams);
i2cParams.bitRate = I2C_400kHz; /* 400KHz */
@@ -373,4 +693,41 @@
return (status);
}
+#if 0
+static int32_t DispApp_InitI2c()
+{
+ int32_t status = FVID2_SOK;
+ uint32_t loopCnt;
+ //uint8_t domain, i2cInst, slaveAddr;
+ //I2C_Params i2cParams;
+ I2C_HwAttrs i2cConfig;
+
+ /* Initialize I2C Driver */
+ for(loopCnt = 0; loopCnt < I2C_HWIP_MAX_CNT; loopCnt++)
+ {
+ I2C_socGetInitCfg(loopCnt, &i2cConfig);
+ i2cConfig.enableIntr = false;
+ I2C_socSetInitCfg(loopCnt, &i2cConfig);
+ }
+
+ /* Initializes the I2C */
+ I2C_init();
+#if 0
+ /* Initializes the I2C Parameters */
+ I2C_Params_init(&i2cParams);
+ i2cParams.bitRate = I2C_400kHz; /* 400KHz */
+
+ Board_fpdUb941GetI2CAddr(&domain, &i2cInst, &slaveAddr);
+
+ /* Configures the I2C instance with the passed parameters*/
+ gI2cHandle = I2C_open(i2cInst, &i2cParams);
+ if(gI2cHandle == NULL)
+ {
+ App_print("\nI2C Open failed!\n");
+ status = FVID2_EFAIL;
+ }
+#endif
+ return (status);
+}
+#endif
patch as attachment, please focus on below files modifications:
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c <set resolution as 1280x480 superframe> ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c <lane-num and lane-speed> ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c <config SERDES>
Q:
1. Could you please confirm <DSI IP interface output 1280x480 superframe parameters> whether the modification is correct or if there are any omissions that have not been modified yet ?
2. My understanding is that the parameters set in these files will be called in the end to configure the DSI D-PHY output 1280x480 image. Please correct me !!!
3. If the thses configuration parameters are set correctly, can you confirm that the DSI interface can output images normally ?
By the way
Application layer colleagues linqiang.huang@ecarxgroup.com will then synchronize the changes (modifications made on TI-DL demo) in this thread !!!
Looking forward to your reply.
Best Regards
Murphy
#ifndef __SOCKET_CONN__
#define __SOCKET_CONN__
#include "stdio.h"
#include "stdlib.h"
#include <sys/socket.h>
#include <sys/types.h>
#include <sys/un.h>
#include <stdint.h>
#define MAX_WIDTH 1280
#define MAX_HEIGHT 480
enum DataType{
RGB_888 = 1,
RGB_565,
RGB_YUV,
};
typedef struct DlpData{
int32_t type;
int32_t length;
uint8_t data[MAX_WIDTH*MAX_HEIGHT*3];
}RgbData_t;
typedef struct DlpInitData{
int32_t lcd_width;
int32_t lcd_height;
int32_t display_width;
int32_t display_height;
}DlpInitData_t;
void *startDataReceiver(void *arg);
int32_t initSocketClient(void);
int32_t initSocket(void);
int32_t sendRGBData(void* rgbData, uint32_t rgbLength);
#endifApplication uses a resolution of 1280*480.
Hi Murphy,
.
1. Could you please confirm <DSI IP interface output 1280x480 superframe parameters> whether the modification is correct or if there are any omissions that have not been modified yet ?
For DSI, it does not matter, it is just single input frame of size 1280x480 and yes, it can support this frame size.
2. My understanding is that the parameters set in these files will be called in the end to configure the DSI D-PHY output 1280x480 image. Please correct me !!!
Did not get the question, which parameter do you mean here? You are setting timing parameters, which will get applied first and display would be started and then input video pipelines would be configured and then will merge two frames and send it out as one single merged frame..
3. If the thses configuration parameters are set correctly, can you confirm that the DSI interface can output images normally ?
yes, if the receiver supports this parameters..
Regarding parameters shared by linqiang.huang@ecarxgroup.com, none of them seems related to DSI configuration. They are more like application level configuration..
Regards,
Brijesh
Hi Brijesh,
Thank you for your reply.
Did not get the question, which parameter do you mean here?
Parameters set in these files:
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/platform/j721e/rtos/common/app_init.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dctrl.c
These two files are used to set LCD timing parameters and DSI lane-num/speed, and finally will be aplied to configure video pipeline and D-PHY to output image from DSI interface like you said. Are these Settings compatible with the DSI interface to output the desired 1280x480 image correctly ?
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_defaults.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/utils/dss/src/app_dss_j721e.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.h
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/board/src/devices/common/common.c
these four files just for SERDES configuration. After receiving the 1280x480 image output from the DSI interface, the SER internally divides into two 640x480 images for the two DES to display on the two screens.
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/pdk_jacinto_08_01_00_36/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_multi_cam/main.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/apps/basic_demos/app_single_cam/app_single_cam_main.c
ti-processor-sdk-rtos-j721e-evm-08_01_00_13/vision_apps/modules/src/app_display_module.c
these four files just Basic Demos for cameras modifications and it worked before.
Now we want to use Image Classification Application demo to output image. please guide us how to achieve this.
Best Regards,
Murphy
Hi Brijesh，
Below is the application sending data "00 00 fe" and printing it on the mcu side.This is the progress so far. Hope it helps
[MCU2_0] 333.225748 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.225850 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.225947 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226043 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226179 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226279 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226376 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226472 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226568 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
[MCU2_0] 333.226664 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
Hi Murphy,
these four files just Basic Demos for cameras modifications and it worked before.
ok, does it mean these configuration/timing parameters are working fine, isn't it? Do you see valid output over DSI with this configuration? Then you shouldnt worry about timing parameters..
Now we want to use Image Classification Application demo to output image. please guide us how to achieve this.
Not sure the output resolution from this demo, does it output 1280x480 resolution? If not, you would require to use scalar in the video pipeline to downscale input image to 1280x480 resolution..
Below is the application sending data "00 00 fe" and printing it on the mcu side.This is the progress so far. Hope it helps
[MCU2_0] 333.225748 s: VX_ZONE_ERROR:| 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe | 00 00 fe |
Sorry did not get it. Are you printing it from the buffer, which is being sent out? Why do you require to print buffer contents? Are you checking also content on the receiver side?
Regards,
Brijesh
Sorry did not get it. Are you printing it from the buffer, which is being sent out? Why do you require to print buffer contents? Are you checking also content on the receiver side?
yes.
ok, but this data is before it goes out of DSS. So not sure how does it help? I think you should check if you are getting these data at the receiver end.
Also please note that data will not remain same at the receiver, you should expect slight change in the data due to format conversion.
Regards,
Brijesh
I think you should check if you are getting these data at the receiver end
please help me to understand the receiver end .
Which method is easier to verify from the receiver end of what you said? (Driver or APP side) Please tell me how to verify it.
Regards,
Murphy
Hi Murphy,
I meant which module is receiving DSI data. Is it some display or LCD or some deserializer based receiver? Do you see correct data on the receiver?
Regards,
Brijesh
