[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board hardware design - Ethernet

Hi Board designers, 

1.Peripherals Supporting Ethernet interface

The CPSW3G and PRU_ICSSG peripherals support ethernet interfaces

2.Number of Ethernet interfaces supported by CPSW3G.

CPSW3G supports 2 external interfaces that could be used a switch or individual MAC.

3.Number of Instances and Ethernet interfaces supported by PRU_ICSSG

x2 instances of PRU_ICSSG are supported by AM64x devices. Each of the PRU_ICSSG instance supports 2 Ethernet interfaces PRU0 and PRU1 

4.Are all 6 Ethernet interfaces supported by any of the AM64x family of devices.

The processor supports up to five concurrent external Ethernet (EPHY) interfaces. Pinmuxing overlaps one of the CPSW3G and PRU_ICSSG1 (PRG1_PRU1).

5.Do all the devices in the Family support the same number of Ethernet interfaces?

The Ethernet interfaces support depends on the device selection. Refer below section of the device specific data sheet

Table 5-1. Device Comparison

6.What PRU_ICSSG functionality is on each AM64x device

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1098260/faq-am6442-what-pru_icssg-functionality-is-on-each-am64x-device/4068272#4068272

7.Any recommendation for using MDIO interfaces.

It is recommended to use the MDIO module available on the CPSW3G and the PRU_ICSSG for the Ethernet interfaces implemented with CPSW3G and PRU_ICSSG peripherals.

8.Is AM64x affected by the MDIO Errata

Before configuring the MDIO interface, see the advisory i2329 MDIO: MDIO interface corruption (CPSW and
PRU-ICSS) of the device-specific silicon errata.
Refer to advisory MDIO: MDIO interface corruption (CPSW and PRU_ICSS) and device-specific silicon errata to
verify if the processor selected is affected by the advisory.
If the selected processor and the silicon revision being used is affected by the silicon errata, there is a work around
implemented by the driver. The driver reads the device JTAG ID and configures the MDIO to use manual (bit
bang) mode.

9.Do you have recommendations on adding series resistors for RGMII interface?

It is recommended to provide provision for series resistors close to the SOC for the TX signals.

Series resistors for the Receive signals are EPHY dependent. It is recommended to provision for series resistors with 0R for enhancements for future use.

10.Are the above series resistor recommendations valid for MII or RMII interface

The Above recommendations for series resistors are valid for these MAC interfaces.

11.Is there any clock recommendations When using Ethernet interface

Refer below section of the device specific data sheet.

Table 7-17. MCU_OSC0 Crystal Circuit Requirements

https://www.ti.com/lit/gpn/am6442

12.Recommendations for using External clock oscillator

7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source

Refer 

https://www.ti.com/tool/TMDS64EVM 

and 

https://www.ti.com/tool/SK-AM64B

for implementation.

13.IO levels supported for Ethernet interface.

The IOs support dual voltage (Either 1.8 V or 3.3 V)

14.Is the RGMII internal delay supported by the processor and is the RGMII internal delay configurable

RGMII_ID is not timed, tested, or characterized. RGMII_ID is enabled by default for TX (Transmit) and the register bit is reserved.

Delay is not implemented for the RX (Receive) path.

15.Can AM64x CPSW handle both 100BASE RMII for one port and 1000BASE RGMII for another port?

CPSW3G allows using mixed RGMII/RMII interface.

16. Can i interface 2 X RMII PHYs with the PHY configured as Master 

RMII_REF_CLK is common to both RMII1 and RMII2. It is recommended to use one of the interface as RMII and the other interface as RGMII for 100M

17. Do you have interfacing recommendations for RMII interface.

Refer below document for guidelines.

https://www.ti.com/lit/an/spracu5b/spracu5b.pdf

An FAQ for the RMII interface guideline is planned and the FAE link will be provided in this FAQ when available.

Regards,

Sreenivasa