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DRA821U: LPDDR4 Single Rank Mode, Dual Rank Layout

Stuart Baker
Genius 10500 points
Part Number: DRA821U

I'm working with a customer that is planning to use a single rank DDR in their design. However, they wish to setup their layout to be compatible with dual rank. They have checked with the DDR vendor (ISSI), and they say it is okay to route the extra CS_1_0, CS_1_1, and CKE_1 signals to their single rank device as the "standard" pins are true no-connect.

What is the state of these three dual rank signals coming from the DRA821U in single rank mode (CS_1_0, CS_1_1, and CKE_1)? Are they actively driven to either a high or low state or are they floating? The concern we have is that if they are floating, they could more negatively effect the other nearby DDR signals in terms of cross-talk. We are hoping all three signals are actively driven either high or low and not floating.

Thanks,

Stuart

  • 0
    TI__Genius 10500 points

    Any thoughts here?

  • +1 in reply to Stuart Baker
    TI__Mastermind 34610 points

    Discussed with design team, and received following feedback: CS / CKE will always be actively driven, and not tri-stated.

  • 0 in reply to Kevin S
    Prodigy 90 points

    So what is the value on CS10, CS11 and CKE1 in the active state? Are the CS values following CS00 and CS01? Is the CKE1 value same as what is on CKE0?

     

    In the LPDDR4 config spreadsheet we define the part as single rank on my board (as we are only using single rank LPDDR4 part for now). So I am interested in knowing the state of these pins in active state while supporting single Rank LPDDR4. We may switch to dual rank LPDDR4 in the future on our board.