I'm working with a customer that is planning to use a single rank DDR in their design. However, they wish to setup their layout to be compatible with dual rank. They have checked with the DDR vendor (ISSI), and they say it is okay to route the extra CS_1_0, CS_1_1, and CKE_1 signals to their single rank device as the "standard" pins are true no-connect.
What is the state of these three dual rank signals coming from the DRA821U in single rank mode (CS_1_0, CS_1_1, and CKE_1)? Are they actively driven to either a high or low state or are they floating? The concern we have is that if they are floating, they could more negatively effect the other nearby DDR signals in terms of cross-talk. We are hoping all three signals are actively driven either high or low and not floating.
Thanks,
Stuart
